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公开(公告)号：US11955512B1
公开(公告)日：2024-04-09
申请号：US17552266
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H01L21/321 , H01L21/768 , H01L49/02
CPC分类号： H01L28/91 , H01L21/3212 , H01L21/76843 , H01L28/92
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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12.发明公开公开(公告)号：US20230246062A1
公开(公告)日：2023-08-03
申请号：US17649534
申请日：2022-01-31
发明人： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC分类号： H01L49/02 , H01L21/324 , H01L21/768 , H01L27/11507 , H01L45/00
CPC分类号： H01L28/57 , H01L21/324 , H01L21/76832 , H01L27/11507 , H01L28/65 , H01L28/75 , H01L45/147
摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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公开(公告)号：US11716858B1
公开(公告)日：2023-08-01
申请号：US17315143
申请日：2021-05-07
发明人： Niloy Mukherjee , Ramamoorthy Ramesh , Sasikanth Manipatruni , James Clarkson , Fnu Atiquzzaman , Gabriel Antonio Paulius Velarde , Jason Y. Wu
IPC分类号： H10B53/30 , H01L27/115 , H01L49/02
摘要： Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.
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公开(公告)号：US11659714B1
公开(公告)日：2023-05-23
申请号：US17315111
申请日：2021-05-07
发明人： Niloy Mukherjee , Ramamoorthy Ramesh , Sasikanth Manipatruni , James Clarkson , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Jason Y. Wu
IPC分类号： H01L27/11507 , H01L27/11502 , H01L49/02 , H01L27/11597 , H01L27/11592 , H01L27/11587
CPC分类号： H01L27/11597 , H01L27/11502 , H01L27/11507 , H01L27/11587 , H01L27/11592 , H01L28/55 , H01L28/57 , H01L28/75
摘要： Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.
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15.发明授权公开(公告)号：US12022662B1
公开(公告)日：2024-06-25
申请号：US17552321
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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公开(公告)号：US12016185B1
公开(公告)日：2024-06-18
申请号：US17552293
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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17.发明授权公开(公告)号：US11985832B1
公开(公告)日：2024-05-14
申请号：US17552323
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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公开(公告)号：US11894417B2
公开(公告)日：2024-02-06
申请号：US17649899
申请日：2022-02-03
发明人： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC分类号： H01L21/768 , H01L21/324 , H10B53/30 , H10N70/20 , H10N70/00 , H01L23/522 , H01L49/02
CPC分类号： H01L28/57 , H01L21/324 , H01L21/76832 , H01L28/65 , H01L28/75 , H10B53/30 , H10N70/8836
摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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19.发明授权公开(公告)号：US11832451B1
公开(公告)日：2023-11-28
申请号：US17396609
申请日：2021-08-06
发明人： Debraj Guhabiswas , Maria Isabel Perez , Jason Y. Wu , James David Clarkson , Gabriel Antonio Paulius Velarde , Niloy Mukherjee , Noriyuki Sato , Amrita Mathuriya , Sasikanth Manipatruni , Ramamoorthy Ramesh
摘要： Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
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公开(公告)号：US11744081B1
公开(公告)日：2023-08-29
申请号：US17315139
申请日：2021-05-07
发明人： Niloy Mukherjee , Ramamoorthy Ramesh , Sasikanth Manipatruni , James Clarkson , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Jason Y. Wu
摘要： Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.
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