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29 条记录 (耗时 0.019 秒)

    Decoupling capacitor for surface mounted chip carrier
    12.
    发明授权
    Decoupling capacitor for surface mounted chip carrier 失效
    表面贴装芯片载体的去耦电容

    公开(公告)号：US4658327A

    公开(公告)日：1987-04-14

    申请号：US763826

    申请日：1985-08-08

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G2/12 ,  H01G4/228 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01G1/14 ,  H01C1/01

    CPC分类号： H01G4/228 ,  H01G2/12 ,  H05K1/0231 ,  H05K1/18 ,  H05K2201/10515 ,  H05K2201/10704 ,  H05K3/3447

    摘要： High frequency noise is decoupled from power supplied to a surface mounted integrated circuit (IC) chip carrier package by installation of a surface mounted decoupling capacitor between the IC chip carrier package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of surface mountable leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a surface mounted integrated circuit (IC) chip carrier package and correspond to the power and ground pin configuration of that package.

    摘要翻译： 通过在IC芯片载体封装和印刷电路板之间安装表面安装的去耦电容器，高频噪声与提供给表面安装集成电路（IC）芯片载体封装的电源分离。 去耦电容器包括夹在一对导体之间并具有从每个导体延伸的多个可表面安装的引线的电介质材料。 根据本发明，去耦电容器被独立地定尺寸并且被配置成配合在表面安装的集成电路（IC）芯片载体封装下，并对应于该封装的电源和接地引脚配置。

    Method for filling vias in ceramic substrates with composite metallic paste
    14.
    发明授权
    Method for filling vias in ceramic substrates with composite metallic paste 失效
    用复合金属膏填充陶瓷衬底通孔的方法

    公开(公告)号：US5707575A

    公开(公告)日：1998-01-13

    申请号：US282055

    申请日：1994-07-28

    申请人： David K. Litt ,  Jorge M. Hernandez

    发明人： David K. Litt ,  Jorge M. Hernandez

    IPC分类号： H01L21/48 ,  H05K1/03 ,  H05K3/40 ,  C04B35/00

    CPC分类号： H01L21/486 ,  H05K3/4061 ,  H05K1/0306 ,  H05K2203/0156 ,  H05K2203/0278 ,  H05K2203/0338

    摘要： A method and apparati for improved filling of via holes wherein compressive force is used to columnate conductive material due to a pseudoplastic thixotropic rheology of the material. Columnating of the material provides for easier and more accurate filling of via holes. Both automated roller apparati and manual methods are provided. The method further includes methods and apparati of removing excess conductive material from substrates after filling the via holes.

    摘要翻译： 一种改进填充通孔的方法，其中压缩力由于材料的假塑性触变流变学而用于对导电材料进行柱状化。 材料的分级提供了更容易和更准确地填充通孔。 提供自动滚筒装置和手动方法。 该方法还包括在填充通孔之后从衬底去除过量的导电材料的方法和装置。

    Multilayer printed wiring board
    15.
    再颁专利
    Multilayer printed wiring board 失效
    多层印刷线路板

    公开(公告)号：USRE35064E

    公开(公告)日：1995-10-17

    申请号：US60877

    申请日：1993-05-12

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G4/20 ,  H05K1/00 ,  H05K1/03 ,  H05K1/16 ,  H05K3/46 ,  H05K1/18 ,  H05K1/11

    CPC分类号： H01G4/20 ,  H05K1/0353 ,  H05K1/162 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K3/4611

    摘要： A multilayer printed wiring board is presented for surface mounting or through hole technology, which includes one or more layers of a high capacitance flexible dielectric sheet material. The dielectric sheet is comprised of a monolayer of multilayer or single layer high dielectric constant (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The board of the present invention alleviates the need for decoupling capacitors, thus resulting in significant, space savings on the board surface.

    摘要翻译： 提供了一种用于表面安装或通孔技术的多层印刷线路板，其包括一层或多层高容量柔性电介质片材料。 电介质片材由布置成平面阵列的单层多层或单层高介电常数（例如陶瓷）芯片或相对较小面积和厚度的颗粒组成。 这些高介电常数芯片间隔开一小段距离。 然后用柔性聚合物/粘合剂填充芯片之间的空间以限定粘合片，聚合物将高电介质（例如陶瓷）芯片的阵列结合在一起。 接下来，阵列（包括聚合物）的相对的平坦表面通过真空金属沉积或溅射进行化学镀或电化，以限定相对的金属化表面。 本发明的电路板减轻了去耦电容器的需要，从而在电路板表面上节省了大量的空间。

    Low impedance bus bar
    17.
    发明授权
    Low impedance bus bar 失效
    低阻母线

    公开(公告)号：US5051542A

    公开(公告)日：1991-09-24

    申请号：US291514

    申请日：1988-12-29

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G4/20 ,  H05K1/00 ,  H05K1/16 ,  H05K3/46

    CPC分类号： H05K1/162 ,  H01G4/20 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K3/4611

    摘要： A bus bar is presented which sandwiches a high capacitance flexible dielectric sheet material between the conductive layers. The high capacitance dielectric sheet is comprised of a monolayer of multilayer or single layer high dielectric (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The whole structure is then sandwiched between two conductive layers. The result is a bus bar with a very low characteristic impedance.

    摘要翻译： 提供了一种母线，其在导电层之间夹着高电容的柔性电介质片材料。 高电容电介质片材由布置成平面阵列的单层多层或单层高电介质（例如陶瓷）芯片或相对较小面积和厚度的颗粒构成。 这些高介电常数芯片间隔开一小段距离。 然后用柔性聚合物/粘合剂填充芯片之间的空间以限定粘合片，聚合物将高电介质（例如陶瓷）芯片的阵列结合在一起。 接下来，阵列（包括聚合物）的相对的平坦表面通过真空金属沉积或溅射进行化学镀或电化，以限定相对的金属化表面。 然后将整个结构夹在两个导电层之间。 结果是具有非常低的特性阻抗的母线。

    High dielectric constant flexible sheet material
    18.
    发明授权
    High dielectric constant flexible sheet material 失效
    高介电常数柔性片材

    公开(公告)号：US4908258A

    公开(公告)日：1990-03-13

    申请号：US226619

    申请日：1988-08-01

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： B32B15/04 ,  H01B3/00 ,  H01G4/12 ,  H01G4/20 ,  H05K1/00 ,  H05K1/16 ,  H05K3/46

    CPC分类号： H05K1/162 ,  H01G4/20 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K3/4611 ,  Y10S428/901 ,  Y10T428/24157 ,  Y10T428/24826 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/252 ,  Y10T428/31678

    摘要： A high capacitance flexible dielectric sheet material is comprised of a monolayer of multilayer or single layer high dielectric (for example ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (for example ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The end result is a relatively flexible high capacitance dielectric film or sheet material which is drillable, platable, printable, etchable, laminable and reliable.

    摘要翻译： 高容量柔性介电片材料由布置成平面阵列的单层多层或单层高电介质（例如陶瓷）芯片或相对较小面积和厚度的颗粒组成。 这些高介电常数芯片间隔开一小段距离。 然后用柔性聚合物/粘合剂填充芯片之间的空间以限定粘合片材，聚合物将高电介质（例如陶瓷）芯片的阵列结合在一起。 接下来，阵列（包括聚合物）的相对的平坦表面通过真空金属沉积或溅射进行化学镀或电化，以限定相对的金属化表面。 最终的结果是相对柔性的高容量电介质膜或片材，其是可钻的，可镀的，可印刷的，可蚀刻的，可层压的和可靠的。

    Temperature stable multilayer capacitor
    19.
    发明授权
    Temperature stable multilayer capacitor 失效
    温度稳定的多层电容器

    公开(公告)号：US4873612A

    公开(公告)日：1989-10-10

    申请号：US226601

    申请日：1988-08-01

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G4/12 ,  H01G4/20 ,  H01G4/258 ,  H01G4/30

    CPC分类号： H01G4/258 ,  H01G4/20 ,  Y10T29/435

    摘要： The temperature characteristics of each of the layers in a multilayer ceramic capacitor are adjusted (through chemical doping of the basic dielectric material) to thereby stagger the temperature characteristics (e.g. curie points). As a result, the composite temperature characteristic of the multilayer structure will be much more stable than that of any individual layer. The temperature characteristics of the individual layers will combine in an additive manner thereby achieving the objective of high capacitance and uniform temperature stability for materials which have high dielectric constant but poor temperature stability. Thus, by properly formulating the composition of the layers of a multilayer ceramic chip capacitor, relative temperature stability of capacitance and high volumetric capacitance efficiency will be achieved.

    摘要翻译： 调整多层陶瓷电容器中的各层的温度特性（通过碱性介电材料的化学掺杂），从而错开温度特性（例如居里点）。 结果，多层结构的复合温度特性将比任何单独层的复合温度特性稳定得多。 各层的温度特性将以添加的方式组合，从而实现了具有高介电常数但温度稳定性差的材料的高电容和均匀温度稳定性的目的。 因此，通过适当地配制多层陶瓷片式电容器的层的组成，可以实现电容的相对温度稳定性和高体积电容效率。