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公开(公告)号：US20190189429A1
公开(公告)日：2019-06-20
申请号：US15848495
申请日：2017-12-20
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , G03F7/42 , G03F7/11
摘要： A surface treatment composition and methods for improving adhesion of an organic layer on a titanium-containing hardmask includes forming a self-assembled monolayer on a surface of the titanium-containing hardmask prior to depositing the organic layer. The self-assembled monolayer is formed from a blend of alkyl phosphonic acids of formula (I): X(CH2)nPOOH2(I), wherein n is 6 to 16 and X is either CH3 or COOH, wherein a ratio of the methyl terminated (CH3) alkyl phosphonic acid to the carboxyl terminated (COOH) alkyl phosphonic acid ranges from 25:75 to 75:25.
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公开(公告)号：US10254652B2
公开(公告)日：2019-04-09
申请号：US16050866
申请日：2018-07-31
IPC分类号： G03F7/004 , G03F7/16 , B82Y40/00 , H01L21/3213 , G03F7/20 , H01L21/027 , G03F7/09 , G03F7/11
摘要： An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.
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公开(公告)号：US11227892B2
公开(公告)日：2022-01-18
申请号：US16443934
申请日：2019-06-18
摘要： A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.
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公开(公告)号：US20210296438A1
公开(公告)日：2021-09-23
申请号：US17343291
申请日：2021-06-09
发明人： Praveen Joseph , Tao Li , Indira Seshadri , Ekmini A. De Silva
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66 , H01L21/311 , H01L21/8238 , H01L27/092 , H01L21/306 , H01L21/02 , H01L21/3065 , H01L21/762
摘要： Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.
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15.发明授权公开(公告)号：US10923401B2
公开(公告)日：2021-02-16
申请号：US16172205
申请日：2018-10-26
发明人： Andrew Greene , Marc Bergendahl , Ekmini A. De Silva , Alex Joseph Varghese , Yann Mignot , Matthew T. Shoudy , Gangadhara Raja Muthinti , Dallas Lea
IPC分类号： H01L21/8234 , H01L21/3205 , H01L29/66 , H01L21/3213
摘要： Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.
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公开(公告)号：US10782613B2
公开(公告)日：2020-09-22
申请号：US15956870
申请日：2018-04-19
IPC分类号： G03F7/20 , C23C16/40 , C08G79/04 , G03F7/16 , G03F7/38 , C09D185/02 , C23C16/455 , H01L21/02 , C23C16/04
摘要： Self-assembled monolayers (SAMs) were selectively prepared on portions of a substrate surface utilizing compounds comprising a hydrogen-bonding group and polymerizable diacetylene group. The SAMs were photopolymerized using ultraviolet light. The pre-polymerized and polymerized SAMs were more effective barriers against metal deposition in an atomic layer deposition process compared to similar compounds lacking these functional groups.
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17.发明申请公开(公告)号：US20200266100A1
公开(公告)日：2020-08-20
申请号：US16277528
申请日：2019-02-15
发明人： Nicole Saulnier , Indira Seshadri , Lawrence A. Clevenger , Leigh Anne H. Clevenger , Gauri Karve , Fee Li Lie , Isabel Cristina Chu , Hosadurga Shobha , Ekmini A. De Silva
IPC分类号： H01L21/768 , H01L21/311
摘要： Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.
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公开(公告)号：US20200135544A1
公开(公告)日：2020-04-30
申请号：US16169121
申请日：2018-10-24
IPC分类号： H01L21/768 , H01L21/027 , H01L21/033 , H01L21/311
摘要： A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer.
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公开(公告)号：US20200051872A1
公开(公告)日：2020-02-13
申请号：US16059319
申请日：2018-08-09
发明人： Jing Guo , Ekmini A. De Silva , Nicolas Loubet , Indira Seshadri , Nelson Felix
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/768 , H01L27/108
摘要： Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
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公开(公告)号：US20200033733A1
公开(公告)日：2020-01-30
申请号：US16044629
申请日：2018-07-25
IPC分类号： G03F7/20 , G03F7/16 , C23C16/30 , C23C16/40 , C23C16/455 , C23C16/56 , H01L21/027 , H01L21/02 , H01L21/67
摘要： Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.
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