公开(公告)号：US10756031B1

公开(公告)日：2020-08-25

申请号：US16409321

申请日：2019-05-10

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Franklin M. Baez ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/34 ,  H01L23/64 ,  H01L49/02 ,  H01L23/04 ,  H01L23/522

Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.

公开(公告)号：US20200176383A1

公开(公告)日：2020-06-04

申请号：US16209013

申请日：2018-12-04

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Steve Ostrander ,  Thomas Weiss ,  Mark W. Kapfhammer ,  Shidong Li

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

公开(公告)号：US10515929B2

公开(公告)日：2019-12-24

申请号：US15948023

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L25/065 ,  H01L23/522 ,  H01L23/13 ,  H01L25/00 ,  H01L23/538

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190312010A1

公开(公告)日：2019-10-10

申请号：US15948038

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190312009A1

公开(公告)日：2019-10-10

申请号：US15948023

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/538 ,  H01L25/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20210242146A1

公开(公告)日：2021-08-05

申请号：US16777169

申请日：2020-01-30

Applicant: International Business Machines Corporation

Inventor： Charles Leon Arvin ,  Karen P. McLaughlin ,  Thomas Anthony Wassick ,  Brian W. Quinlan

IPC: H01L23/00

Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

公开(公告)号：US10957650B2

公开(公告)日：2021-03-23

申请号：US16546912

申请日：2019-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Karen P. McLaughlin ,  Brian W. Quinlan ,  Thomas Weiss

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.

公开(公告)号：US10892249B2

公开(公告)日：2021-01-12

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20200185156A1

公开(公告)日：2020-06-11

申请号：US16211345

申请日：2018-12-06

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Sylvain Pharand ,  Bhupender Singh ,  Brian W. Quinlan

IPC: H01G4/38 ,  H01G4/228 ,  H01L23/66

Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

公开(公告)号：US20190312011A1

公开(公告)日：2019-10-10

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/13

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.