公开(公告)号：US10734282B2

公开(公告)日：2020-08-04

申请号：US16141181

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mihir K Roy ,  Mathew J Manusharow ,  Mark Hlad

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/288 ,  H05K3/46 ,  H01L23/552 ,  H01L23/498 ,  H01L23/36

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

公开(公告)号：US10312007B2

公开(公告)日：2019-06-04

申请号：US13711149

申请日：2012-12-11

Applicant: Intel Corporation

Inventor： Mihir K Roy ,  Mathew J Manusharow ,  Harold Ryan Chase

IPC: H01F17/00

Abstract: A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.

公开(公告)号：US10163557B2

公开(公告)日：2018-12-25

申请号：US14973115

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mihir K Roy ,  Mathew J Manusharow ,  Yikang Deng

IPC: H01F5/00 ,  H01F27/28 ,  C25D5/16 ,  C25D5/48 ,  C25D7/00 ,  H01F27/255 ,  H01F41/02 ,  H01F41/04 ,  H01F17/00

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

公开(公告)号：US09955589B2

公开(公告)日：2018-04-24

申请号：US13717048

申请日：2012-12-17

Applicant: Intel Corporation

Inventor： Mihir K Roy ,  Matthew J Manusharow

IPC: H05K3/46 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H05K3/10 ,  H01L23/538 ,  H05K1/18

Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

公开(公告)号：US09741686B2

公开(公告)日：2017-08-22

申请号：US15056625

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mathew J Manusharow ,  Mihir K Roy

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/0652 ,  H01L21/56 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18162 ,  H05K1/183 ,  H05K1/186 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.