公开(公告)号：US10163557B2

公开(公告)日：2018-12-25

申请号：US14973115

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mihir K Roy ,  Mathew J Manusharow ,  Yikang Deng

IPC: H01F5/00 ,  H01F27/28 ,  C25D5/16 ,  C25D5/48 ,  C25D7/00 ,  H01F27/255 ,  H01F41/02 ,  H01F41/04 ,  H01F17/00

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

公开(公告)号：US09741686B2

公开(公告)日：2017-08-22

申请号：US15056625

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mathew J Manusharow ,  Mihir K Roy

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/0652 ,  H01L21/56 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18162 ,  H05K1/183 ,  H05K1/186 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.