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公开(公告)号:US12021986B2
公开(公告)日:2024-06-25
申请号:US17562700
申请日:2021-12-27
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Ming-Chih Tung , Hsin-Lung Wu , Juin-Ming Lu , Bo-Xuan Zhu
Abstract: A neural network (NN) processing method is provided. An AI (artificial intelligence) compiler code of an AI compiler is transformed to a garbled circuit code by performing following steps. A circuit graph of a garbled circuit having logic gates corresponding to the garbled circuit code is sent to an electrical device by a server. Key codebooks for candidate gates corresponding to each logic gate are creating by the electrical device. Garbled truth tables for the candidate gates corresponding to each logic pate are generated and transmitted to the server by the electrical device through using OT (Oblivious Transfer) protocol. A target garbled truth table of each logic gate is generated by the server. Afterward, an NN model is encrypted according to the key codebooks by the electrical device and a compiled NN model of an encrypted NN model are generated by the server.
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公开(公告)号:US11657273B2
公开(公告)日:2023-05-23
申请号:US16728341
申请日:2019-12-27
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Yao-Hua Chen , Jing-Jia Liou , Chih-Tsun Huang , Juin-Ming Lu
Abstract: An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.
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13.
公开(公告)号:US10268519B2
公开(公告)日:2019-04-23
申请号:US14983086
申请日:2015-12-29
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Heng-Yi Chen , Chung-Ho Chen , Chen-Chieh Wang , Juin-Ming Lu , Chun-Hung Lai , Hsun-Lun Huang
Abstract: A scheduling method is provided. The method includes: recording a next instruction and a ready state of each thread group in a scoreboard; determining whether there is any ready thread group whose ready state is affirmative; determining whether a load/store unit is available, wherein the load/store unit is configured to access a data memory unit; when the load/store unit is available, determining whether the ready thread groups include a data access thread group, wherein the next instruction of the data access thread group is related to accessing the data memory unit; selecting a target thread group from the data access thread groups; and dispatching the target thread group to the load/store unit for execution.
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公开(公告)号:US10896276B2
公开(公告)日:2021-01-19
申请号:US15843375
申请日:2017-12-15
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Mei-Ling Chi , Yao-Hua Chen , Hsun-Lun Huang , Juin-Ming Lu
IPC: G06F30/3323 , G06F13/16 , G06F13/28 , G06F30/3312 , G06F1/28 , G06F119/12
Abstract: Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.
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15.
公开(公告)号:US09953393B2
公开(公告)日:2018-04-24
申请号:US14983494
申请日:2015-12-29
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Arthur Marmin , Chun-Hung Lai , Hsun-Lun Huang , Juin-Ming Lu
CPC classification number: G06T1/20 , G06F11/3664 , G06K9/00 , G06K9/6223 , G06K9/6269 , G06K9/6287
Abstract: An analyzing method and an analyzing system for graphics process are provided. The analyzing method includes the following steps. A graphics application program is provided and a plurality of graphics parameters of the graphics application program are obtained. The graphics application program is classified to be at least one of a plurality of groups according to the graphics parameters. A plurality weighting coefficients are obtained. A total loading of a graphics processing unit for performing the graphics application program is calculated according to the weighting coefficients and the graphics parameters.
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公开(公告)号:US09842180B2
公开(公告)日:2017-12-12
申请号:US14585864
申请日:2014-12-30
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Ting-Shuo Hsu , Jing-Jia Liou , Jih-Sheng Shen , Juin-Ming Lu
CPC classification number: G06F17/5045 , G06F1/32 , G06F15/7825 , G06F17/5031 , G06F17/5077 , G06F17/5081 , G06F2217/84 , Y02D10/12 , Y02D10/13
Abstract: A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.
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公开(公告)号:US09626733B2
公开(公告)日:2017-04-18
申请号:US14551089
申请日:2014-11-24
Applicant: Industrial Technology Research Institute
Inventor: Hsu-Yao Huang , I-Hsuan Lu , Tai-Hua Lu , Shau-Yin Tseng , Juin-Ming Lu
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.
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