Neural network processing method and server and electrical device therefor

    公开(公告)号:US12021986B2

    公开(公告)日:2024-06-25

    申请号:US17562700

    申请日:2021-12-27

    CPC classification number: H04L9/32 G06F8/41 G06N3/063

    Abstract: A neural network (NN) processing method is provided. An AI (artificial intelligence) compiler code of an AI compiler is transformed to a garbled circuit code by performing following steps. A circuit graph of a garbled circuit having logic gates corresponding to the garbled circuit code is sent to an electrical device by a server. Key codebooks for candidate gates corresponding to each logic gate are creating by the electrical device. Garbled truth tables for the candidate gates corresponding to each logic pate are generated and transmitted to the server by the electrical device through using OT (Oblivious Transfer) protocol. A target garbled truth table of each logic gate is generated by the server. Afterward, an NN model is encrypted according to the key codebooks by the electrical device and a compiled NN model of an encrypted NN model are generated by the server.

    Timing esimation method and simulator

    公开(公告)号:US10896276B2

    公开(公告)日:2021-01-19

    申请号:US15843375

    申请日:2017-12-15

    Abstract: Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.

    Data-processing apparatus and operation method thereof

    公开(公告)号:US09626733B2

    公开(公告)日:2017-04-18

    申请号:US14551089

    申请日:2014-11-24

    CPC classification number: G06T1/20

    Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

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