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11.发明申请ADVANCED ULTRA LOW K SICOH DIELECTRICS PREPARED BY BUILT-IN ENGINEERED PORE SIZE AND BONDING STRUCTURED WITH CYCLIC ORGANOSILICON PRECURSORS 有权高级超低K SICOH电介质由内置工程孔径和结合结构与循环有机硅前驱体公开(公告)号：US20150279667A1
公开(公告)日：2015-10-01
申请号：US14225810
申请日：2014-03-26
CPC分类号： H01L21/02126 , H01B3/46 , H01L21/02203 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348
摘要： Disclosed herein is an ultra-low dielectric (k) film and methods of making thereof. A ultra-low k film has a covalently bonded network comprising atoms of silicon, oxygen, carbon, and hydrogen, a cyclotrisilane structure, and a plurality of pores having a pore size distribution (PSD) of less than about 1.1 nanometers (nm). The ultra-low k film has a k value of less than about 2.4 and at least about 28 atomic percent of carbon.
摘要翻译： 本文公开了一种超低介电（k）薄膜及其制造方法。 超低k膜具有包含硅，氧，碳和氢的原子，环状硅烷结构和孔径分布（PSD）小于约1.1纳米（nm）的多个孔的共价键合网络。 超低k膜具有小于约2.4的k值和至少约28原子％的碳。
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12.发明授权公开(公告)号：US09040411B2
公开(公告)日：2015-05-26
申请号：US14194036
申请日：2014-02-28
IPC分类号： H01L21/4763 , H01L21/31 , H01L21/02 , C23C16/32 , C23C16/56 , H01L21/768
CPC分类号： H01L21/02263 , C23C16/325 , C23C16/56 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834
摘要： A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.
摘要翻译： 提供了形成碳浓度大于或等于约30原子％C并且介电常数小于或等于约4.5的富碳碳化硅状电介质膜的方法。 电介质膜可以任选地包括氮。 当存在氮时，富含碳的碳化硅状电介质膜具有小于或等于约5原子％氮的浓度氮。
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公开(公告)号：US08980715B2
公开(公告)日：2015-03-17
申请号：US14012448
申请日：2013-08-28
发明人： Alfred Grill , Seth L. Knupp , Son V. Nguyen , Vamsi K. Paruchuri , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L29/78 , H01L23/532 , H01L21/02 , H01L29/66
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02247 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/76283 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/481 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
摘要翻译： 提供具有氮化硅（SiN）和氮氧化硅（SiNO）膜用作封盖层，衬垫，间隔壁和蚀刻停止层以及半导体纳米器件的其它部件的多层电介质结构。 例如，半导体结构包括具有包括一个或多个SiN层和一个或多个SiNO层的多层电介质材料的多层电介质结构。 多层电介质结构中的介电材料层的厚度在约0.5纳米至约3纳米的范围内。
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公开(公告)号：US20140256153A1
公开(公告)日：2014-09-11
申请号：US14012448
申请日：2013-08-28
发明人： Alfred Grill , Seth L. Knupp , Son V. Nguyen , Vamsi K. Paruchuri , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/02
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02247 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/76283 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/481 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
摘要翻译： 提供具有氮化硅（SiN）和氮氧化硅（SiNO）膜用作封盖层，衬垫，间隔壁和蚀刻停止层以及半导体纳米器件的其它部件的多层电介质结构。 例如，半导体结构包括具有包括一个或多个SiN层和一个或多个SiNO层的多层电介质材料的多层电介质结构。 多层电介质结构中的介电材料层的厚度在约0.5纳米至约3纳米的范围内。
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公开(公告)号：US10256185B2
公开(公告)日：2019-04-09
申请号：US15793020
申请日：2017-10-25
发明人： Lawrence A. Clevenger , Roger A. Quon , Hosadurga K. Shobha , Terry A. Spooner , Wei Wang , Chih-Chao Yang
IPC分类号： H01L23/522 , H01L21/3065 , H01L23/532 , H01L23/528 , H01L21/768
摘要： A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.
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公开(公告)号：US10224241B2
公开(公告)日：2019-03-05
申请号：US15825889
申请日：2017-11-29
发明人： Daniel C. Edelstein , Son V. Nguyen , Takeshi Nogami , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522 , H01L21/02
摘要： Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
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公开(公告)号：US09966337B1
公开(公告)日：2018-05-08
申请号：US15459684
申请日：2017-03-15
发明人： Benjamin D. Briggs , Lawrence A. Clevenger , Huai Huang , Christopher J. Penny , Michael Rizzolo , Hosadurga K. Shobha
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/76879 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53295
摘要： A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer interconnects arrayed across the dielectric layer with the second metallization layer interconnects adjacent one another and surrounded by the first metallization layer interconnects and a cap. The first and second metallization layer interconnects have respective upper surfaces defining a first plane and a second plane recessed from the first plane, respectively. The cap is disposed on exposed surfaces of the second metallization layer interconnects and portions of the dielectric layer adjacent to the second metallization layer interconnects.
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公开(公告)号：US09947581B2
公开(公告)日：2018-04-17
申请号：US15214760
申请日：2016-07-20
发明人： Daniel C. Edelstein , Son V. Nguyen , Takeshi Nogami , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522 , H01L21/02
CPC分类号： H01L21/76879 , H01L21/02068 , H01L21/02172 , H01L21/02244 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76865 , H01L21/76873 , H01L21/76888 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
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公开(公告)号：US09947579B2
公开(公告)日：2018-04-17
申请号：US15417390
申请日：2017-01-27
发明人： Daniel C. Edelstein , Son V. Nguyen , Takeshi Nogami , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/768 , H01L21/02 , H01L23/532
CPC分类号： H01L21/76879 , H01L21/02068 , H01L21/02172 , H01L21/02244 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76865 , H01L21/76873 , H01L21/76888 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
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公开(公告)号：US20180090436A1
公开(公告)日：2018-03-29
申请号：US15793020
申请日：2017-10-25
发明人： Lawrence A. Clevenger , Roger A. Quon , Hosadurga K. Shobha , Terry A. Spooner , Wei Wang , Chi-Chao Yang
IPC分类号： H01L23/522 , H01L23/532 , H01L21/3065 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/3065 , H01L21/768 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L23/53295
摘要： A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.
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