公开(公告)号：US20180293205A1

公开(公告)日：2018-10-11

申请号：US15482796

申请日：2017-04-09

申请人： Intel Corporation

发明人： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F13/40 ,  G11C5/02

CPC分类号： G06F15/8007 ,  G06F9/3004 ,  G06F13/00 ,  G06F13/4027 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20

摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US20230061670A1

公开(公告)日：2023-03-02

申请号：US17978573

申请日：2022-11-01

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06N3/08 ,  G06F9/38 ,  G06N3/063 ,  G06F9/30 ,  G06N20/00 ,  G06N3/04 ,  G06F9/50 ,  G06F7/483

摘要： One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

公开(公告)号：US20230039729A1

公开(公告)日：2023-02-09

申请号：US17963539

申请日：2022-10-11

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. MacPherson ,  John C. Weast ,  Justin E. Gottschlich ,  Jingyi Jin ,  Barath Lakshmanan ,  Chandrasekaran Sakthivel ,  Michael S. Strickland ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Balaji Vembu ,  Ping T. Tang ,  Anbang Yao ,  Tatiana Shpeisman ,  Xiaoming Chen

IPC分类号： G05B13/02 ,  G05D1/00 ,  G06N3/04 ,  G06N3/02 ,  G06N5/04 ,  G06N20/00

摘要： Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230027203A1

公开(公告)日：2023-01-26

申请号：US17826674

申请日：2022-05-27

申请人： Intel Corporation

发明人： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC分类号： G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US11468541B2

公开(公告)日：2022-10-11

申请号：US17720804

申请日：2022-04-14

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anhang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06F7/483 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06T15/00

摘要： Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple or mixed precisions and dynamic ranges.

公开(公告)号：US11461107B2

公开(公告)日：2022-10-04

申请号：US16227645

申请日：2018-12-20

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Tatiana Shpeisman ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/50 ,  G06N3/00

摘要： One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

公开(公告)号：US11409537B2

公开(公告)日：2022-08-09

申请号：US15819167

申请日：2017-11-21

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Tatiana Shpeisman ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F13/40 ,  G06F13/42 ,  G06N20/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

摘要： One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.

公开(公告)号：US11080811B2

公开(公告)日：2021-08-03

申请号：US16446398

申请日：2019-06-19

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC分类号： G06T1/20 ,  G06F3/14 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T15/00 ,  G09G5/36 ,  G06T15/04

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 16-bit and/or 32 bit floating-point elements.

公开(公告)号：US20210124579A1

公开(公告)日：2021-04-29

申请号：US17115989

申请日：2020-12-09

申请人： Intel Corporation

发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC分类号： G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

公开(公告)号：US10726514B2

公开(公告)日：2020-07-28

申请号：US15581167

申请日：2017-04-28

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00 ,  G06F3/14 ,  G06T1/60 ,  G06T15/00

摘要： One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.