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公开(公告)号：US10860709B2
公开(公告)日：2020-12-08
申请号：US16024547
申请日：2018-06-29
申请人： Intel Corporation
发明人： Michael Lemay , David M. Durham , Michael E. Kounavis , Barry E. Huntley , Vedvyas Shanbhogue , Jason W. Brandt , Josh Triplett , Gilbert Neiger , Karanvir Grewal , Baiju V. Patel , Ye Zhuang , Jr-Shian Tsai , Vadim Sukhomlinov , Ravi Sahita , Mingwei Zhang , James C. Farwell , Amitabh Das , Krishna Bhuyan
摘要： Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.
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公开(公告)号：US10713177B2
公开(公告)日：2020-07-14
申请号：US15260893
申请日：2016-09-09
申请人： Intel Corporation
发明人： Gilbert Neiger , Baiju V. Patel , Gur Hildesheim , Ron Rais , Andrew V. Anderson , Jason W. Brandt , David M. Durham , Barry E. Huntley , Raanan Sade , Ravi L. Sahita , Vedvyas Shanbhogue , Arumugam Thiyagarajah
IPC分类号： G06F12/1009 , G06F12/14 , G06F9/455
摘要： A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.
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公开(公告)号：US10599547B2
公开(公告)日：2020-03-24
申请号：US15827890
申请日：2017-11-30
申请人： Intel Corporation
发明人： Gilbert Neiger , Andrew V. Anderson , Richard A. Uhlig , David M. Durham , Ronak Singhal , Xiangbin Wu , Sailesh Kottapalli
摘要： Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
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公开(公告)号：US10282306B2
公开(公告)日：2019-05-07
申请号：US15861364
申请日：2018-01-03
申请人： INTEL CORPORATION
发明人： Krystof C. Zmudzinski , Siddhartha Chhabra , Uday R. Savagaonkar , Simon P. Johnson , Rebekah M. Leslie-Hurd , Francis X. McKeen , Gilbert Neiger , Raghunandan Makaram , Carlos V. Rozas , Amy L. Santoni , Vincent R. Scarlata , Vedvyas Shanbhogue , Ilya Alexandrovich , Ittai Anati , Wesley H. Smith , Michael Goldsmith
IPC分类号： G06F12/14 , G06F9/455 , G06F12/109 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/1045
摘要： A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
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公开(公告)号：US10180911B2
公开(公告)日：2019-01-15
申请号：US15620663
申请日：2017-06-12
申请人： Intel Corporation
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/00 , G06F12/1027 , G06F12/0875 , G06F12/1045 , G06F9/455 , G06F12/02 , G06F12/1036 , G06F12/1009
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US20180357179A1
公开(公告)日：2018-12-13
申请号：US16005385
申请日：2018-06-11
申请人： Intel Corporation
IPC分类号： G06F12/1036 , G06F9/455 , G06F9/48 , G06F12/02 , G06F12/0804 , G06F12/0891 , G06F12/1045 , G06F12/109 , G06F12/12 , G06F12/123 , G06F12/1027
CPC分类号： G06F12/1036 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1027 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/1024 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/651 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/70
摘要： In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
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公开(公告)号：US10120805B2
公开(公告)日：2018-11-06
申请号：US15408774
申请日：2017-01-18
申请人： Intel Corporation
发明人： Rebekah M. Leslie-Hurd , Francis X. McKeen , Carlos V. Rozas , Gilbert Neiger , Asit Mallick , Ittai Anati , Ilya Alexandrovich , Vedvyas Shanbhogue , Somnath Chakrabarti
IPC分类号： G06F9/30 , G06F12/0837 , G06F9/455 , G06F12/1045
摘要： A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.
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公开(公告)号：US20180239713A1
公开(公告)日：2018-08-23
申请号：US15861364
申请日：2018-01-03
申请人： INTEL CORPORATION
发明人： Krystof C. Zmudzinski , Siddhartha Chhabra , Uday R. Savagaonkar , Simon P. Johnson , Rebekah M. Leslie-Hurd , Francis X. McKeen , Gilbert Neiger , Raghunandan Makaram , Carlos V. Rozas , Amy L. Santoni , Vincent R. Scarlata , Vedvyas Shanbhogue , Ilya Alexandrovich , Ittai Anati , Wesley H. Smith , Michael Goldsmith
IPC分类号： G06F12/1009 , G06F12/1027 , G06F9/455 , G06F12/14 , G06F12/109
CPC分类号： G06F12/1009 , G06F9/455 , G06F9/45558 , G06F12/1027 , G06F12/1036 , G06F12/1045 , G06F12/109 , G06F12/1441 , G06F2009/45583 , G06F2212/1016 , G06F2212/1052 , G06F2212/151 , G06F2212/657 , G06F2212/684
摘要： A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
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公开(公告)号：US20180203801A1
公开(公告)日：2018-07-19
申请号：US15408774
申请日：2017-01-18
申请人： Intel Corporation
发明人： Rebekah M. Leslie-Hurd , Francis X. McKeen , Carlos V. Rozas , Gilbert Neiger , Asit Mallick , Ittai Anati , Ilya Alexandrovich , Vedvyas Shanbhogue , Somnath Chakrabarti
IPC分类号： G06F12/0837 , G06F9/30 , G06F9/455 , G06F12/1045
CPC分类号： G06F12/0837 , G06F9/30003 , G06F9/45558 , G06F12/1063 , G06F2009/45583 , G06F2009/45591 , G06F2212/152 , G06F2212/60 , G06F2212/621 , G06F2212/68
摘要： A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.
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公开(公告)号：US20180060099A1
公开(公告)日：2018-03-01
申请号：US15251425
申请日：2016-08-30
申请人： INTEL CORPORATION
CPC分类号： G06F9/45558 , G06F11/221 , G06F11/3027 , G06F11/3055 , G06F12/1045 , G06F12/1475 , G06F2009/45579 , G06F2009/45583 , G06F2009/45591 , G06F2212/1008 , G06F2212/151 , G06F2212/152 , G06F2212/68
摘要： A processor may include a register to store a bus-lock-disable bit and an execution unit to execute instructions. The execution unit may receive an instruction that includes a memory access request. The execution may further determine that the memory access request requires acquiring a bus lock, and, responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system.
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