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公开(公告)号：US06414619B1
公开(公告)日：2002-07-02
申请号：US09945926
申请日：2001-09-04
Applicant: Eric J. Swanson
Inventor： Eric J. Swanson
IPC: H03M112
Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.
Abstract translation: 提供了一种自动量程模数转换系统。 该系统可以包括用于放大模拟输入和模拟输入的估计之间的差的数字可编程前置放大器。 前置放大器可以耦合到模数转换器，用于将前置放大器输出转换成数字信号。 该系统还可以包括用于确定给定模拟输入的最佳增益和模拟输入估计的数字域预测器或估计逻辑。 多个信号输入通道可以耦合到模数转换系统。 自动量程估计可以根据样本或逐个频道进行。
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公开(公告)号：US06310518B1
公开(公告)日：2001-10-30
申请号：US09429002
申请日：1999-10-29
Applicant: Eric J. Swanson
Inventor： Eric J. Swanson
IPC: H03G320
Abstract: A programmable gain preamplifier is provided which has a low temperature drift and good dynamic range characteristics. The programmable gain preamplifier provides a programmable gain of the difference between two input signals (Ain and Ain′ for example). One of the input signals (Ain′) may be an estimation of the other input signal (Ain). The estimation input signal (or a signal related to the estimated input) may be generated by the use of a reference voltage and a first resistor string. More particularly, the reference voltage and the first resistor string may operate as a digital to analog converter (DAC) that converts a digital estimation signal to an analog estimation voltage. The analog estimation voltage operates as an analog voltage that is a function of (or the same as) the analog Ain′ estimation signal. The first resistor string may provide the estimation voltage without loading the resistor string. Thus, the first resistor string may be simultaneously utilized by other circuitry, such as for example, a downstream ADC. The programmable preamplifier gain may be set by the use of a second resistor string and digitally programmable switches. Contacts to the resistors strings may be placed outside of the current path of each resistor string to provide highly stable resistor strings having a very low temperature drift. In one preamplifier embodiment, some or all of the opamps may chopper stabilized opamps, at least one opamp may be a current feedback opamp, the resistor strings may be at least 64 resistors long and programmable gains from 1 to 32 may be provided.
Abstract translation: 提供了一种可编程增益前置放大器，具有低温度漂移和良好的动态范围特性。 可编程增益前置放大器提供两个输入信号（例如Ain和Ain'）之间差异的可编程增益。 输入信号（Ain'）中的一个可以是另一个输入信号（Ain）的估计。 可以通过使用参考电压和第一电阻串来产生估计输入信号（或与估计输入相关的信号）。 更具体地，参考电压和第一电阻器串可以作为将数字估计信号转换为模拟估计电压的数模转换器（DAC）来操作。 模拟估计电压作为模拟电压作为模拟电压估计信号的（或相同）的函数。 第一电阻器串可以提供估计电压而不加载电阻器串。 因此，第一电阻器串可以被其他电路同时使用，例如下游ADC。 可编程前置放大器增益可以通过使用第二电阻器串和数字可编程开关来设定。 与电阻器串的接触可以放置在每个电阻器串的电流路径之外，以提供具有非常低的温度漂移的高度稳定的电阻器串。 在一个前置放大器实施例中，一些或所有运算放大器可以斩波稳定的运算放大器，至少一个运算放大器可以是电流反馈运算放大器，电阻器串可以是至少64个电阻器长，并且可以提供从1到32的可编程增益。
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公开(公告)号：US06288664B1
公开(公告)日：2001-09-11
申请号：US09442026
申请日：1999-11-17
Applicant: Eric J. Swanson
Inventor： Eric J. Swanson
IPC: H03M118
Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.
Abstract translation: 提供了一种自动量程模数转换系统。 该系统可以包括用于放大模拟输入和模拟输入的估计之间的差的数字可编程前置放大器。 前置放大器可以耦合到模数转换器，用于将前置放大器输出转换成数字信号。 该系统还可以包括用于确定给定模拟输入的最佳增益和模拟输入估计的数字域预测器或估计逻辑。 多个信号输入通道可以耦合到模数转换系统。 自动量程估计可以根据样本或逐个频道进行。
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14.发明授权
公开(公告)号：US5319370A
公开(公告)日：1994-06-07
申请号：US937642
申请日：1992-08-31
Applicant: Bruce D. Signore , Eric J. Swanson
Inventor： Bruce D. Signore , Eric J. Swanson
CPC classification number: H03M1/1047 , G12B13/00 , G01R35/005
Abstract: A method and apparatus for calibration of errors in the analog reference voltage input of an analog-to-digital converter. A monolithic reference voltage generator is provided to generate the analog reference which includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14). The trim circuit (14) provides a temperature compensation for the output of the bandgap voltage reference (50). The system is operable in a calibration mode to measure temperatures during a burn-in procedure and calculate necessary information to determine compensation factors and store these in the EEPROM (60). This temperature data is extracted from the EEPROM (60) and output to a serial I/O port (64), compensation factors determined and then stored back in the EEPROM (60). The delta-sigma A/D converter (52) in the run mode then makes temperature measurements for use by the multiplier/accumulator circuit (74) in determining the appropriate compensation data to extract from the EEPROM (60) to trim the output of the bandgap voltage reference circuit (50).
Abstract translation: 一种用于校准模拟 - 数字转换器的模拟参考电压输入中的误差的方法和装置。 提供单片参考电压发生器以产生模拟基准，其包括输出未整流电压和温度电压的带隙电压基准（50）。 未经校验的电压和温度电压被输入到Δ-ΣA / D转换器（52），其具有通过数字滤波器（54）处理的输出，以在数据总线（58）上输出数据以存储在EEPROM（60 ）。 EEPROM（60）可以在一种模式下操作以存储温度历史数据，并且在另一模式下存储温度补偿数据。 在一种模式中，从EEPROM（60）检索温度补偿参数并由乘法器/累加器电路（74）利用来产生作为数字字输出的补偿系数到用于控制微调电路（14）的DAC（76） ）。 微调电路（14）为带隙电压基准（50）的输出提供温度补偿。 该系统在校准模式下可操作以在老化过程期间测量温度，并计算确定补偿因子的必要信息并将其存储在EEPROM（60）中。 该温度数据从EEPROM（60）提取并输出到串行I / O端口（64），然后确定补偿因子并将其存储回EEPROM（60）。 运行模式中的Δ-ΣA / D转换器（52）然后进行温度测量，以供乘法器/累加器电路（74）使用以确定适当的补偿数据以从EEPROM（60）提取以修剪 带隙电压参考电路（50）。
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公开(公告)号：US4618815A
公开(公告)日：1986-10-21
申请号：US700029
申请日：1985-02-11
Applicant: Eric J. Swanson
Inventor： Eric J. Swanson
CPC classification number: G05F3/262
Abstract: An MOS current mirror arrangement is disclosed wherein selected ones of the input and output transistors are designed to have a threshold voltage, V.sub.T1, greater in magnitude that associated with standard MOS devices. The larger threshold voltage thus eases the requirement that the turn-on voltage, V.sub.ON, remain less than the threshold voltage V.sub.T, for the devices to remain in the active region of operation. Since a minimum value of V.sub.T is useful for some applications (fast processing and operation at high temperatures) the use of mixed thresholds allows both requirements to be met by adjusting the thresholds of selected devices associated with these different requirements. The difference in threshold voltages can be attained simply by adjusting the threshold adjust implant mask to protect selected devices from the ion implantation conventionally used to decrease the magnitude of the threshold voltage.
Abstract translation: 公开了MOS电流镜布置，其中输入和输出晶体管中的选定的晶体管被设计成具有与标准MOS器件相关联的幅度更大的阈值电压VT1。 因此，较大的阈值电压使得开启电压VON保持小于阈值电压VT的要求，以使器件保持在有效的操作区域中。 由于VT的最小值对于一些应用（在高温下的快速处理和操作）是有用的，因此使用混合阈值允许通过调整与这些不同要求相关联的所选设备的阈值来满足这两个要求。 阈值电压的差异可以简单地通过调整阈值调整注入掩模来实现，以保护所选择的器件免于常规用于减小阈值电压幅度的离子注入。
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Patent Agency Ranking
公开(公告)号：US4518926A
公开(公告)日：1985-05-21
申请号：US451025
申请日：1982-12-20
Applicant: Eric J. Swanson
Inventor： Eric J. Swanson
Abstract: An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410). The gates (106, 206, 308, 310) are coupled together as an input node. In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier. In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier. Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300). A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400).
Abstract translation: 增强模式（104,204,404）和耗尽模式（102,202,402）对的N沟道MOS晶体管的漏极 - 源极传导路径串联连接并设置有偏置电流装置（120,220,404） 306，410）。 门（106,206,308,310）作为输入节点耦合在一起。 在一个实施例（100）中，它们的体区域是源极连接的，并且输出端（118）来自增强模式器件（104）的源极，以获得源极跟随器配置放大器。 在第二实施例（200）中，输出（218）取自耗尽型装置（202）的漏极（208），以获得公共源配置放大器。 两个源极跟随器对（302,304）被并联连接以形成差分输入电压放大器级（300）。 与额外的增强模式晶体管（406）组合公开了形成电流镜（400）的公共源对（402,404）。
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公开(公告)号：US06452519B1
公开(公告)日：2002-09-17
申请号：US09432502
申请日：1999-11-02
Applicant: Eric J. Swanson
Inventor： Eric J. Swanson
IPC: H03M110
Abstract: A successive approximation ADC is provided. Contacts to a resistor string may be placed outside of the current path of the resistor string to provide a highly stable resistor string having a very low temperature drift. The resistor string may be utilized to calibrate a successive approximation ADC. The resistor string may also be a portion of a resistor array of a resistor and capacitor array ADC. The resistor string may be calibrated with a calibration ADC having a resolution greater than the resistor string. The calibration ADC may be a delta sigma ADC.
Abstract translation: 提供逐次逼近ADC。 与电阻串的接触可以放置在电阻串的电流路径之外，以提供具有非常低的温度漂移的高度稳定的电阻串。 电阻串可用于校准逐次逼近ADC。 电阻器串还可以是电阻器和电容器阵列ADC的电阻器阵列的一部分。 可以使用具有大于电阻串的分辨率的校准ADC校准电阻器串。 校准ADC可以是ΔigmaADC。
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18.发明授权
公开(公告)号：US5351050A
公开(公告)日：1994-09-27
申请号：US970693
申请日：1992-11-03
Applicant: Charles D. Thompson , Eric J. Swanson
Inventor： Charles D. Thompson , Eric J. Swanson
Abstract: The thermal noise generated through the feedback capacitor of a delta-sigma modulator is attenuated by transferring a reference voltage through the capacitor in two separate steps during each sampling period. This permits a reduction in the size of the feedback capacitor, thereby reducing thermal noise, without increasing the voltage on the switching capacitors on the summing node side of the feedback capacitors which would induce degradation due to hot electron effects.
Abstract translation: 通过Δ-Σ调制器的反馈电容产生的热噪声通过在每个采样周期内以两个分开的步骤传送参考电压通过电容器来衰减。 这允许减小反馈电容器的尺寸，从而降低热噪声，而不会增加反馈电容器的求和节点侧的开关电容器上的电压，这将导致由于热电子效应引起的退化。
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19.发明授权
公开(公告)号：US5257026A
公开(公告)日：1993-10-26
申请号：US870270
申请日：1992-04-17
Applicant: Charles D. Thompson , Salvador R. Bernadas , Nicholas R. van Bavel , Eric J. Swanson
Inventor： Charles D. Thompson , Salvador R. Bernadas , Nicholas R. van Bavel , Eric J. Swanson
Abstract: A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input.
Abstract translation: 用于校准多电平Δ-Σ调制器（12）中的非线性的校准方法和装置包括在输入端上的校准多路复用器（10），用于在校准模式中选择用于输入到Δ-Σ调制器的零电压 （12）。 Δ-Σ调制器（12）具有三个电平，即+1,0，-1，向处理器（32）输入的+1电平，以及输入到处理器（34）的-1电平。 处理器（34）的输出被输入到补偿电路（14），该补偿电路将由-1处理器（34）产生的值偏移系数增量。 然后，补偿电路（14）的输出被输入到也接收处理器（32）的输出的求和结（36）的负输入，提供数字输出的求和结（36）的输出。 处理器（32）和（34）通过单独的累加器来实现，所述累加器在相关的滤波器系数和地之间切换存储在ROM（35）中的滤波器系数。 增量系数存储在块（16）中，并且在校准周期期间由增量处理器（39）产生。 当校准多路复用器（10）将输入设置为零时，Δ处理器（39）接收补偿电路（14）的输出和来自求和结（36）的数字输出。 控制电路（40）控制总体操作，其中响应于线路（30）上的外部信号或内部产生的信号启动校准操作。 校准后，delta系数的值被冻结，校准多路复用器（10）选择模拟输入。
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20.发明授权Variable decimation architecture for a delta-sigma analog-to-digital converter 失效DELTA-SIGMA模拟数字转换器的可变分频结构
公开(公告)号：US5157395A
公开(公告)日：1992-10-20
申请号：US664034
申请日：1991-03-04
Applicant: Bruce Del Signore , Eric J. Swanson , Jeffrey M. Klaas , David L. Medlock
Inventor： Bruce Del Signore , Eric J. Swanson , Jeffrey M. Klaas , David L. Medlock
CPC classification number: H03H17/0294 , H03H17/0664
Abstract: An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.
Abstract translation: 模数转换器包括Δ-Σ调制器（10），其输出被数字滤波器部分滤波。 数字滤波器部分包括具有固定抽取比率的第一固定抽取滤波器（12）和随后的可变抽取滤波器部分（14）和输出低通滤波器部分（16）。 固定可变抽取滤波器部分（14）包括具有不同采样率的处理数据的单个FIR滤波器（24）。 递归控制器（26）接收外部配置输入以确定提供所需抽取比所需的通过过滤器（24）的通过次数。
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