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    SYSTEM FOR GENERATING A MULTIPLE PHASE CLOCK
    13.
    发明申请
    SYSTEM FOR GENERATING A MULTIPLE PHASE CLOCK 失效
    用于生成多个相位时钟的系统

    公开(公告)号：US20090045882A1

    公开(公告)日：2009-02-19

    申请号：US11838282

    申请日：2007-08-14

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0315 ,  H03K5/15026 ,  H03K5/1506

    摘要： A system for generating a multiple phase clock. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M.

    摘要翻译： 一种用于产生多相时钟的系统。 该系统包括用于产生多相的环形振荡器结构。 该结构包括两个或多个单元振荡器，每个单位振荡器由具有M级的环形振荡器实现。 该结构还包括耦合两个或多个单元振荡器以产生多个相位的水平环路。 产生的相数等于单位振荡器数与M的乘积。

    Clock generation circuit and method of generating clock signals
    14.
    发明申请
    Clock generation circuit and method of generating clock signals 审中-公开
    时钟产生电路和产生时钟信号的方法

    公开(公告)号：US20070090867A1

    公开(公告)日：2007-04-26

    申请号：US11472322

    申请日：2006-06-22

    申请人： Kyu-hyoun Kim

    发明人： Kyu-hyoun Kim

    IPC分类号： G06F1/04

    CPC分类号： G06F1/04 ,  H03K5/133 ,  H03K5/1504 ,  H03K5/151 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0891

    摘要： Clock generation circuit and method of generating clock signals. The clock generation circuit includes an inverter directly receiving an external clock signal and outputting an inverted external clock signal, M (where M is an integer ≧1) loop circuits arranged in series, the first loop circuit receiving the inverted external clock signal, each of the N loop circuits having n (where n is an integer ≧2) nodes, each of the M−1 loop circuits generating n intermediate internal clock signals, each at a corresponding one of the n nodes, wherein a frequency of the n intermediate internal clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal; and n sets of inverters, each including M−1 inverters connected in series, each of the M−1 inverters receiving a corresponding intermediate internal clock signal from a previous loop circuit and outputting a corresponding intermediate internal clock signal to a next loop circuit.

    摘要翻译： 时钟产生电路和产生时钟信号的方法。 时钟发生电路包括直接接收外部时钟信号并输出​​反相外部时钟信号M（其中M是整数> = 1）的串联布置的回路电路的逆变器，第一环路电路接收反相的外部时钟信号，每个 具有n（其中n是整数> = 2）个节点的N个环路电路中的每个M-1个环路电路产生n个中间内部时钟信号，每个在n个节点中的相应一个，其中n个 中间内部时钟信号是外部时钟信号和反相外部时钟信号的频率的倍数; 以及n组反相器，各自包括串联连接的M-1个反相器，每个M-1个反相器从前一个环路电路接收相应的中间内部时钟信号，并将相应的中间内部时钟信号输出到下一个环路电路。

    Double data rate synchronous dynamic random access memory semiconductor device
    15.
    发明授权
    Double data rate synchronous dynamic random access memory semiconductor device 失效
    双数据速率同步动态随机存取存储器半导体器件

    公开(公告)号：US07038972B2

    公开(公告)日：2006-05-02

    申请号：US10793209

    申请日：2004-03-04

    申请人： Sung-min Seo ,  Chi-wook Kim ,  Kyu-hyoun Kim

    发明人： Sung-min Seo ,  Chi-wook Kim ,  Kyu-hyoun Kim

    IPC分类号： G01C8/00

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

    摘要： A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.

    摘要翻译： 提供了一种双倍数据速率（“DDR”）同步动态随机存取存储器（“SDRAM”）半导体器件，其防止当将数据写入DDR SDRAM半导体器件时从数据读取和写入DDR SDRAM半导体器件的数据之间的冲突 ，其包括延迟锁定环（“DLL”）电路，时钟信号控制单元，输出单元和输出控制单元，其中DLL电路补偿输入时钟信号的偏斜并产生输出时钟信号; 当读出存储在DDR SDRAM半导体器件中的数据时，时钟信号控制单元接收到激活的读取信号，当DLL电路对输入时钟信号执行锁定操作时激活的DLL锁定信号和输出时钟信号，并且输出 当读取信号或DLL锁定信号有效时，输出时钟信号; 输出单元缓冲存储在DDR SDRAM半导体器件中的数据，并将数据与从时钟信号控制单元输出的输出时钟信号同步地输出到DDR SDRAM半导体器件的外部; 并且输出控制单元接收从时钟信号控制单元输出的输出时钟信号和读取信号，并将读出的信号与从时钟信号控制单元输出的输出时钟信号同步输出到输出单元。

    Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information
    16.
    发明授权
    Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information 有权

    公开(公告)号：US07035148B2

    公开(公告)日：2006-04-25

    申请号：US10631412

    申请日：2003-07-30

    申请人： Hoe-ju Chung ,  Kyu-hyoun Kim

    发明人： Hoe-ju Chung ,  Kyu-hyoun Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222

    摘要： An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.

    Output driver and method thereof
    17.
    发明申请
    Output driver and method thereof 失效

    公开(公告)号：US20060076980A1

    公开(公告)日：2006-04-13

    申请号：US11176396

    申请日：2005-07-08

    申请人： Kyu-hyoun Kim ,  Chang-hyun Kim

    发明人： Kyu-hyoun Kim ,  Chang-hyun Kim

    IPC分类号： H03K19/094 ,  H03K19/0175

    CPC分类号： H03K19/0013 ,  H03K19/018514

    摘要： An output driver and method thereof. In the method, a current may be adjusted to adjust a power consumption in response to a change in a data rate. A first example output driver may include at least one transistor receiving at least one input signal, at least one resistor connected between the at least one transistor and a first voltage and a tail current source connected between the at least one transistor and a second voltage, the tail current source controlling a given current level of at least one signal based at least in part on the given data rate. A second example output driver may include a first differential amplification unit, including a first tail current source, receiving first and second input signals and a second differential amplification unit, including a second tail current source, receiving third and fourth input signals, at least one of the first and second tail current sources controlling a given current level of at least one signal based at least in part on the given data rate.

    Semiconductor memory device having partially controlled delay locked loop
    18.
    发明授权
    Semiconductor memory device having partially controlled delay locked loop 失效
    具有部分控制的延迟锁定环的半导体存储器件

    公开(公告)号：US06954094B2

    公开(公告)日：2005-10-11

    申请号：US10645018

    申请日：2003-08-21

    申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

    发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/06

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A semiconductor memory device having a partially controlled delay locked loop includes a delay locked loop and a control signal generator. The control signal generator generates a first control signal and a second control signal, which are responsive to first through fifth mode selection signals for selecting operation modes of the semiconductor memory, device to partially turn the delay locked loop on or off. If the first control signal or the second control signal is activated, a portion of the delay locked loop to which the first or second control signal is applied is turned off. If the first control signal or the second control signal is deactivated, a portion of the delay locked loop to which the first or second control signal is applied is turned on. If the first mode selection signal is activated, only the second control signal is activated. If the second mode selection signal is activated, the first and second control signals are deactivated. If at least one of the third through fifth mode selection signals is activated, the first and second control signals are activated. Since the semiconductor memory device includes a built-in delay locked loop which is partially turned on or off, current consumption of the semiconductor memory device can be reduced.

    摘要翻译： 具有部分控制的延迟锁定环路的半导体存储器件包括延迟锁定环路和控制信号发生器。 所述控制信号发生器产生第一控制信号和第二控制信号，所述第一控制信号和第二控制信号响应于第一至第五模式选择信号，用于选择半导体存储器的操作模式，以部分地将延迟锁定环打开或关闭。 如果第一控制信号或第二控制信号被激活，则施加第一或第二控制信号的延迟锁定环路的一部分被关闭。 如果第一控制信号或第二控制信号被去激活，则施加第一或第二控制信号的延迟锁定环路的一部分被接通。 如果第一模式选择信号被激活，则只有第二控制信号被激活。 如果第二模式选择信号被激活，则第一和第二控制信号被去激活。 如果第三至第五模式选择信号中的至少一个被激活，则第一和第二控制信号被激活。 由于半导体存储器件包括部分导通或截止的内置延迟锁定环，所以可以减少半导体存储器件的电流消耗。

    Input buffer capable of reducing input capacitance seen by input signal
    19.
    发明申请
    Input buffer capable of reducing input capacitance seen by input signal 失效
    输入缓冲器能够减少输入信号所看到的输入电容

    公开(公告)号：US20050068067A1

    公开(公告)日：2005-03-31

    申请号：US10949165

    申请日：2004-09-24

    申请人： Kyu-hyoun Kim

    发明人： Kyu-hyoun Kim

    IPC分类号： H03K5/08 ,  G11C7/10 ,  H03F1/56 ,  H03K5/02 ,  H03K5/153 ,  H03K17/00 ,  H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018514 ,  H03K5/023 ,  H03K19/018585

    摘要： Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input signal and a second input signal and outputs an output signal as the result of the comparison; a second differential amplifier which compares the sizes of the first input signal and a reference voltage and outputs a second output signal as the result of the comparison; and a third differential amplifier which compares the sizes of the second input signal and the reference voltage and outputs a third output signal as the result of the comparison, wherein the first differential amplifier shares transistors, to which the first and second input signals are input, with the second and third differential amplifiers. The first differential amplifier operates only in a differential operation mode, and the second and third differential amplifiers operate only in a single operation mode. The phase of the first input signal is opposite to the phase of the second input signal, and the first and second input signals are different signals in the single operation mode. Accordingly, an input buffer is advantageous in that both a differential signal pair and single-ended signals can be received and output and the input capacitance of the input buffer seen by the input signals can be reduced.

    摘要翻译： 提供了输入缓冲器，其输入电容呈现给输入信号可以减少。 输入缓冲器包括第一差分放大器，其比较第一输入信号和第二输入信号的大小，并输出作为比较结果的输出信号; 比较第一输入信号和参考电压的大小的第二差分放大器，并作为比较结果输出第二输出信号; 以及第三差分放大器，其比较所述第二输入信号和所述参考电压的大小，并且作为比较的结果输出第三输出信号，其中所述第一差分放大器共享输入所述第一和第二输入信号的晶体管， 与第二和第三差分放大器。 第一差分放大器仅在差分工作模式下工作，第二和第三差分放大器仅在单个操作模式下工作。 第一输入信号的相位与第二输入信号的相位相反，并且第一和第二输入信号在单个操作模式中是不同的信号。 因此，输入缓冲器的优点在于可以接收和输出差分信号对和单端信号，并且可以减少由输入信号看到的输入缓冲器的输入电容。

    Interface circuit and signal clamping circuit using level-down shifter
    20.
    发明申请
    Interface circuit and signal clamping circuit using level-down shifter 失效
    接口电路和信号钳位电路采用降档移位器

    公开(公告)号：US20050017783A1

    公开(公告)日：2005-01-27

    申请号：US10890493

    申请日：2004-07-13

    申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

    发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

    IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H04L25/45 ,  H03K3/037

    CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

    摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

    摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。