公开(公告)号：US07035148B2

公开(公告)日：2006-04-25

申请号：US10631412

申请日：2003-07-30

申请人： Hoe-ju Chung ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Kyu-hyoun Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222

摘要： An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.

公开(公告)号：US06693842B2

公开(公告)日：2004-02-17

申请号：US10108671

申请日：2002-03-28

申请人： Hoe-ju Chung ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Kyu-hyoun Kim

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/108

摘要： A semiconductor device having a plurality of output signals is provided. The semiconductor device includes a plurality of PMOS transistors each having a drain of connected to a predetermined node and a source supplied with a first power voltage. A plurality of first buffers are connected to the gates of the plurality of PMOS transistors. A plurality of NMOS transistors each have a drain connected to the predetermined node, and a source supplied with a first ground voltage. A plurality of second buffers are connected to gates of the plurality of NMOS transistors. The plurality of first buffers are supplied with the first ground voltage, the plurality of second buffers are supplied with the first power voltage, and a signal output from a previous portion of the semiconductor device is input into the first and second buffers at predetermined time intervals. As a result, skewing of the output signals is reduced.

摘要翻译： 提供具有多个输出信号的半导体器件。 半导体器件包括多个PMOS晶体管，每个具有连接到预定节点的漏极和提供有第一电源电压的源极。 多个第一缓冲器连接到多个PMOS晶体管的栅极。 多个NMOS晶体管各自具有连接到预定节点的漏极，并且源极被提供有第一接地电压。 多个第二缓冲器连接到多个NMOS晶体管的栅极。 多个第一缓冲器被提供有第一接地电压，多个第二缓冲器被提供有第一电源电压，并且从半导体器件的前一部分输出的信号以预定的时间间隔被输入到第一和第二缓冲器 。 结果，输出信号的偏移减小了。

公开(公告)号：US06590434B2

公开(公告)日：2003-07-08

申请号：US10191413

申请日：2002-07-10

申请人： Hoe-ju Chung ,  Tae-seong Jang ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Tae-seong Jang ,  Kyu-hyoun Kim

IPC分类号： H03H1126

CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00091 ,  H03L7/0814

摘要： A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

公开(公告)号：US07133318B2

公开(公告)日：2006-11-07

申请号：US11339120

申请日：2006-01-23

申请人： Hoe-ju Chung ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Kyu-hyoun Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222

摘要： An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.

摘要翻译： 输出驱动器根据包括操作时钟信号的频率信息的CAS等待时间信息或根据通过检测操作时钟信号的频率而获得的频率信息有效地控制输出信号的转换速率。 输出驱动器包括输出端子，上拉输出端子的上拉驱动器和向下拉输出端子的下拉驱动器。 此外，输出驱动器还包括存储半导体存储器件的CAS等待时间信息的模式寄存器集（MRS）。 响应于CAS延迟信息，上拉驱动器和下拉驱动器的驱动能力是不同的。 输出驱动器可以包括检测并存储半导体存储器件的工作频率的频率检测器。 在这种情况下，上拉驱动器和下拉驱动器的驱动能力响应于从频率检测器输出的输出信号而变化。

公开(公告)号：US20060120180A1

公开(公告)日：2006-06-08

申请号：US11339120

申请日：2006-01-23

申请人： Hoe-ju Chung ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Kyu-hyoun Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222

摘要： An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.

公开(公告)号：US08054663B2

公开(公告)日：2011-11-08

申请号：US12264356

申请日：2008-11-04

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

摘要翻译： 多芯片封装存储器包括产生关于参考处理变化定义的至少一个参考信号的接口芯片和经由垂直连接路径电连接到接口芯片的多个存储器芯片，并经由 垂直连接路径，其中堆叠的多个存储器芯片中的每个存储器芯片的特征在于处理变化，并且主动地补偿与参考信号相关的所述处理变化。

公开(公告)号：US07296110B2

公开(公告)日：2007-11-13

申请号：US11071586

申请日：2005-03-04

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/4243

摘要： Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

摘要翻译： 提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。 存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控​​制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。

公开(公告)号：US08117485B2

公开(公告)日：2012-02-14

申请号：US12379276

申请日：2009-02-18

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F1/12

CPC分类号： G11C29/56012

摘要： Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal.

摘要翻译： 提供了一种用于无缝切换的存储器系统。 存储器系统包括第一至第m个芯片，其中m是自然数，以菊链的形式连接并被配置为传输信号和数据中的至少一个，第一至第m个芯片的第（k-1）个芯片 ，其中k是自然数，2＆nlE; k＆nlE; m，被配置为输出与第（k-1）个芯片的第（k-1）个测试数据和第（k-1）个芯片之间的相位差相对应的第（k-1） 第k个芯片的第k个测试数据，第k个芯片包括时钟相位控制单元，其被配置为控制接收到的时钟信号的相位并将相位控制的时钟信号输出为第k个时钟信号，其中 第k个芯片的时钟相位控制单元响应第（k-1）个检测信号输出第k个时钟信号。

公开(公告)号：US07913000B2

公开(公告)日：2011-03-22

申请号：US12186040

申请日：2008-08-05

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

摘要： A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

摘要翻译： 公开了一种使用复合读取缓冲器操作的堆叠式存储装置。 堆叠式存储装置包括具有主缓冲器和多个存储装置的接口装置，每个存储装置具有装置读缓冲器。 还公开了包含一个或多个堆叠存储器装置的系统和执行读取操作的相关方法。

公开(公告)号：US07734967B2

公开(公告)日：2010-06-08

申请号：US11863500

申请日：2007-09-28

申请人： Hoe-ju Chung ,  Yun-sang Lee

发明人： Hoe-ju Chung ,  Yun-sang Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/12015 ,  G11C2029/3602

摘要： A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

摘要翻译： 具有测试模式和正常模式的半导体存储器件包括倍频器和测试命令序列发生器。 倍频器在测试模式下接收测试时钟信号，并产生多个内部测试时钟信号，每个内部测试时钟信号的频率等于正常模式下的工作时钟信号的频率。 测试时钟信号的频率低于操作时钟信号的频率。 测试命令序列发生器响应于测试模式中的内部测试时钟信号而产生至少一个命令信号。 所述至少一个命令信号对应于待测量的半导体存储器件的至少一个操作定时参数。 倍频器可以包括锁相环（PLL）或延迟锁定环（DLL）。