公开(公告)号：US07422917B2

公开(公告)日：2008-09-09

申请号：US11102998

申请日：2005-04-11

Applicant: Daniel Xu

Inventor： Daniel Xu

IPC: H01L21/00

CPC classification number: H01L45/06 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

Abstract translation: 相变存储器可以具有涂覆有绝缘体的锥形下电极。 涂覆的锥形电极用作用于自对准沟槽蚀刻的掩模，以电隔离相邻字线。 在一些实施例中，锥形下电极可以形成在多个掺杂区域上，并且各向同性蚀刻可以用于使电极逐渐变细以及部分下面的掺杂区域。

公开(公告)号：US20060063297A1

公开(公告)日：2006-03-23

申请号：US11272308

申请日：2005-11-10

Applicant: Daniel Xu ,  Tyler Lowery

Inventor： Daniel Xu ,  Tyler Lowery

IPC: H01L21/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/144 ,  Y10S257/91

Abstract: A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.

公开(公告)号：US06869841B2

公开(公告)日：2005-03-22

申请号：US10384667

申请日：2003-03-11

Applicant: Daniel Xu

Inventor： Daniel Xu

IPC: G11C16/02 ,  H01L45/00 ,  H01L21/8242 ,  H01L21/00

CPC classification number: G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell may be formed with a carbon-containing interfacial layer that heats a phase-change material. By forming the phase-change material in contact, in one embodiment, with the carbon containing interfacial layer, the amount of heat that may be applied to the phase-change material, at a given current and temperature, may be increased. In some embodiments, the performance of the interfacial layer at high temperatures may be improved by using a wide band gap semiconductor material such as silicon carbide.

Abstract translation: 相变存储器单元可以形成有加热相变材料的含碳界面层。 通过在一个实施方案中通过形成相变材料与含碳界面层，可以增加在给定电流和温度下施加到相变材料的热量。 在一些实施方案中，可以通过使用宽带隙半导体材料如碳化硅来改善界面层在高温下的性能。

公开(公告)号：US20050032269A1

公开(公告)日：2005-02-10

申请号：US10633881

申请日：2003-08-04

Applicant: Daniel Xu ,  Tyler Lowrey ,  Jong-Won Lee ,  Kyu Min ,  Donghui Lu ,  Jenn Chow

Inventor： Daniel Xu ,  Tyler Lowrey ,  Jong-Won Lee ,  Kyu Min ,  Donghui Lu ,  Jenn Chow

IPC: H01L21/06 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L45/16 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1293 ,  H01L45/144

Abstract: A planarized surface may be formed by initially forming an aperture through an insulating layer. The insulating layer and its aperture may be conformally coated with a conductive material that ultimately acts as a planarization stop. The conductive material may then be covered with another insulator that fills the remainder of the aperture. Thereafter, the structure may be planarized down to the conductive layer that acts as a planarization stop.

Abstract translation: 可以通过最初通过绝缘层形成孔而形成平坦化表面。 绝缘层及其孔可以共形地涂覆有最终用作平坦化停止的导电材料。 然后可以用填充孔的其余部分的另一绝缘体覆盖导电材料。 此后，该结​​构可以平坦化为用作平坦化停止的导电层。

公开(公告)号：US06673700B2

公开(公告)日：2004-01-06

申请号：US09895020

申请日：2001-06-30

Applicant: Charles H. Dennison ,  Guy C. Wicker ,  Tyler A. Lowrey ,  Stephen J. Hudgens ,  Chien Chiang ,  Daniel Xu

Inventor： Charles H. Dennison ,  Guy C. Wicker ,  Tyler A. Lowrey ,  Stephen J. Hudgens ,  Chien Chiang ,  Daniel Xu

IPC: H01L21326

CPC classification number: H01L27/2463 ,  G11C13/0004 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.

Abstract translation: 一种方法，包括在小于衬底上的接触区域的整个部分上形成牺牲层，所述牺牲层具有限定在所述接触区域上的边缘的厚度，在所述间隔物上形成间隔层，所述隔离层符合形状 的第一牺牲层，使得间隔层包括邻近第一牺牲层边缘的接触区域上的边缘部分，去除牺牲层，同时将间隔物层的边缘部分保持在接触区域上方，形成介于第 接触区域，去除边缘部分，并且将可编程材料形成到以前由边缘部分占据的接触区域。 一种包括可编程材料体积，导体和设置在所述可编程材料体积与所述导体之间的电极的装置，所述电极在一端与所述可编程材料的体积相连接的接触区域，其中所述接触面积小于 一端的表面积。

公开(公告)号：US06667900B2

公开(公告)日：2003-12-23

申请号：US10034331

申请日：2001-12-28

Applicant: Tyler Lowrey ,  Daniel Xu

Inventor： Tyler Lowrey ,  Daniel Xu

IPC: G11C1115

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

Abstract: Briefly, in accordance with an embodiment of the invention, a method and an apparatus to read a phase change memory is provided, wherein the method includes zero biasing unselected memory cells during reading of a selected memory cell.

Abstract translation: 简而言之，根据本发明的实施例，提供一种读取相变存储器的方法和装置，其中该方法包括在读取所选择的存储单元期间对未选择的存储单元进行零偏置。

公开(公告)号：US06563164B2

公开(公告)日：2003-05-13

申请号：US09780805

申请日：2001-02-08

Applicant: Tyler A. Lowrey ,  Daniel Xu ,  Chien Chiang ,  Patrick J. Neschleba

Inventor： Tyler A. Lowrey ,  Daniel Xu ,  Chien Chiang ,  Patrick J. Neschleba

IPC: H01L4700

CPC classification number: H01L27/101 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a first resistivity value and a second material having a different second resistivity value formed by exposing the first material to a gaseous ambient.

公开(公告)号：US08536637B2

公开(公告)日：2013-09-17

申请号：US12959279

申请日：2010-12-02

Applicant: Daniel Xu ,  Roger Lee

Inventor： Daniel Xu ,  Roger Lee

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer.

Abstract translation: 一种用于制造闪存器件的方法包括在衬底中形成阱区，沉积覆盖阱区的栅极电介质层，以及沉积覆盖栅极电介质层的第一多晶硅层。 该方法还包括沉积覆盖在第一多晶硅层上的介电层，并沉积覆盖介电层的第二多晶硅层以形成堆叠层。 该方法同时对堆叠层进行图案以形成第一闪存单元，其包括覆盖在第一多晶硅层的第一部分上的介电层的第一部分上的第二多晶硅层的第一部分并且形成选择器件，其包括 覆盖在第一多晶硅层的第二部分上的介电层的第二部分上的第二多晶硅层的第二部分。 该方法还包括使用离子注入形成源极/漏极区域。 通过向第一多晶硅层的第二部分施加电压来激活选择装置。

公开(公告)号：US20070192643A1

公开(公告)日：2007-08-16

申请号：US11490839

申请日：2006-07-21

Applicant: Shi Henry Li ,  Daniel Xu

Inventor： Shi Henry Li ,  Daniel Xu

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151

Abstract: A system and method for adjusting power consumption of a USB-based device. The system includes a power supply configured to generate a first supply voltage, a controller configured to receive the first supply voltage and generate a control signal, and a USB component configured to receive the control signal and in response operate in a first USB mode or a second USB mode. The controller is further configured to process information associated with the first supply voltage and a predetermined threshold voltage. If the first supply voltage is higher than the predetermined threshold voltage, the control signal represents a first logic state. If the first supply voltage is lower than the predetermined threshold voltage, the control signal represents a second logic state.

Abstract translation: 一种用于调整基于USB设备的功耗的系统和方法。 该系统包括被配置为产生第一电源电压的电源，被配置为接收第一电源电压并产生控制信号的控制器，以及被配置为接收控制信号并响应于第一USB模式或 第二个USB模式。 控制器还被配置为处理与第一电源电压和预定阈值电压相关联的信息。 如果第一电源电压高于预定阈值电压，则控制信号表示第一逻辑状态。 如果第一电源电压低于预定阈值电压，则控制信号表示第二逻辑状态。

公开(公告)号：US20050180191A1

公开(公告)日：2005-08-18

申请号：US11102998

申请日：2005-04-11

Applicant: Daniel Xu

Inventor： Daniel Xu

IPC: H01L45/00 ,  G11C11/22

CPC classification number: H01L45/06 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.