Bottom up electroplating with release layer

    公开(公告)号:US10957628B2

    公开(公告)日:2021-03-23

    申请号:US16592065

    申请日:2019-10-03

    Abstract: A method for producing a conductive through-via, including applying a seed layer on a surface of a first substrate, and forming a surface modification layer on at least one of the seed layer and a second substrate. Next, the second substrate is bonded to the first substrate with the surface modification layer to form an assembly. A conductive release layer is formed in the at least one through-via by placing a conductive release material into the at least one through-via. The conductive release layer is present on the seed layer and in the at least one through-via. A conductive metal material is applied to the at least one through-via, and the second substrate is removed from the assembly after applying the conductive metal material to the at least one through via.

    HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY

    公开(公告)号:US20200165160A1

    公开(公告)日:2020-05-28

    申请号:US16776663

    申请日:2020-01-30

    Abstract: According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

    HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY

    公开(公告)号:US20210407896A1

    公开(公告)日:2021-12-30

    申请号:US17470519

    申请日:2021-09-09

    Abstract: According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

    METHODS FOR FORMING THIN FILM TRANSISTORS ON A GLASS SUBSTRATE AND LIQUID CRYSTAL DISPLAYS FORMED THEREFROM

    公开(公告)号:US20210018780A1

    公开(公告)日:2021-01-21

    申请号:US17040073

    申请日:2019-03-26

    Abstract: A thin film transistor (TFT) liquid crystal display (LCD) comprises a plurality of image pixels demarcated between an overlying liquid crystal display layer and an underlying glass substrate. Each image pixel comprises a dedicated top-gate TFT disposed over the glass substrate. Each top-gate thin film transistor comprises a process sensitive semiconductor layer disposed over the glass substrate, and a source electrode and a drain electrode disposed over the process sensitive semiconductor layer. The process sensitive semiconductor layer forms a process sensitive semiconductor active layer between the source electrode and the drain electrode and an active layer protection film is disposed over the process sensitive semiconductor active layer. A gate dielectric layer is disposed over the active layer protection film between the source electrode and the drain electrode and a gate electrode is disposed over the gate dielectric layer.

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