公开(公告)号：US20150255031A1

公开(公告)日：2015-09-10

申请号：US14366534

申请日：2013-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao ,  Zhongyuan Wu ,  Liye Duan

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/067 ,  G09G2320/043 ,  G11C19/28

Abstract: Provided are a shift register unit and a gate driver circuit, which are configured to suppress output errors caused by the drifts in the threshold voltages and the interval existed in the operation of pulling the output terminal, and thus to enhance stability of the shift register unit. The shift register unit comprises: an input module, a first output module, a pull-down driving module, a pull-down module and a first output discharging unit. The pull-down driving module is connected to the first clock signal input terminal and the second clock signal input terminal, and configured to provide the first clock signal to a first pull-down node in response to the first clock signal, provide the second clock signal to a second pull-down node in response to the second clock signal, provide a first low voltage signal to the first pull-down node and the second pull-down node in response to the voltage signal at the pull-up node, provide the first low voltage signal to the second pull-down node in response to a voltage signal at the first pull-down node, and provide the first low voltage signal to the first pull-down node in response to a voltage signal at the second pull-down node.

Abstract translation: 提供了一种移位寄存器单元和栅极驱动器电路，其被配置为抑制由阈值电压中的漂移和拉动输出端子的操作中存在的间隔引起的输出误差，从而增强移位寄存器单元的稳定性 。 移位寄存器单元包括：输入模块，第一输出模块，下拉驱动模块，下拉模块和第一输出放电单元。 下拉驱动模块连接到第一时钟信号输入端和第二时钟信号输入端，并被配置为响应于第一时钟信号将第一时钟信号提供给第一下拉节点，提供第二时钟 响应于第二时钟信号向第二下拉节点发送信号，响应于上拉节点处的电压信号向第一下拉节点和第二下拉节点提供第一低电压信号，提供 所述第一低电压信号响应于所述第一下拉节点处的电压信号而被提供给所述第二下拉节点，并且响应于所述第二拉动期间的电压信号将所述第一低电压信号提供给所述第一下拉节点 下降节点。

公开(公告)号：US10373538B2

公开(公告)日：2019-08-06

申请号：US15168775

申请日：2016-05-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao ,  Zhongyuan Wu

IPC: G09G3/00 ,  G09G3/3258 ,  G09G3/3266

Abstract: A judging method of array test reliability, comprising: Step 1, taking at least one of organic light emitting backplanes subjected to an array test as a sample substrate; Step 2, performing a scan on pixels of the sample substrate row by row and providing a data voltage signal; Step 3, detecting a current that is output to an anode of each pixel from a pixel circuit layer; Step 4, comparing the current that is output to the anode of each pixel from the pixel circuit layer with a predefined current, judging that the pixel is a defective pixel when the two are inconsistent; Step 5, comparing a judgment result of each pixel with a test result of the array test, judging that the array test is reliable when the two are consistent, judging that the array test is unreliable when the two are inconsistent.

公开(公告)号：US09954070B2

公开(公告)日：2018-04-24

申请号：US14913581

申请日：2015-07-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Longyan Wang ,  Yongqian Li ,  Kun Cao ,  Quanhu Li ,  Jingwen Yin ,  Baoxia Zhang ,  Cuili Gai ,  Zhongyuan Wu ,  Gang Wang

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/45 ,  H01L29/786 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/443 ,  H01L21/4763 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/45 ,  H01L21/28575 ,  H01L21/32134 ,  H01L21/443 ,  H01L21/47635 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78681 ,  H01L29/7869

Abstract: A thin film transistor, a manufacturing method thereof, and a display device are provided. The thin film transistor includes a gate electrode (21), an active layer (23), a source electrode (241) and a drain electrode (242). The source electrode (241) and the drain electrode (242) are formed of at least two materials, the forming materials of the source electrode (241) and the drain electrode (242) can create a cell reaction in a corresponding etching solution so as to be etched, and material of the active layer (23) is not corroded by the etching solution. With the thin film transistor and manufacturing method thereof according to embodiments of the invention, a problem that an active layer is liable to be corroded in an etching procedure of a source electrode and a drain electrode can be solved, and thus the thin film transistor device can be manufactured by using a back channel etch process. Consequently, the process number for manufacture of the thin film transistor is decreased, and the manufacturing cost is saved.

公开(公告)号：US09852685B2

公开(公告)日：2017-12-26

申请号：US14646179

申请日：2014-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liye Duan ,  Zhongyuan Wu ,  Lirong Wang ,  Kun Cao

IPC: G09G3/30 ,  G06F3/038 ,  G09G3/3233 ,  G09G3/3291

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/0866 ,  G09G2310/0289 ,  G09G2320/0233 ,  G09G2320/0626 ,  G09G2330/021

Abstract: There are provided a pixel circuit and a driving method thereof, and a display apparatus. The pixel circuit comprises: a first transistor (T1), a second transistor (T2), a third transistor (T3), a storage capacitor (C1) and a light emitting device (L). A gate of the first transistor (T1) is connected to a first control signal terminal (S1), and a first electrode thereof is connected to a data signal terminal (DATA); a gate of the second transistor (T2) is connected to a second electrode of the first transistor (T1), a first electrode thereof is connected to a second electrode of the third transistor (T3), and a second electrode thereof is connected to a first terminal of the light emitting device (L); a gate of the third transistor (3) is connected to a second control signal terminal (S2), and a first electrode thereof is connected to a first power supply signal terminal (ELVDD); one terminal of the storage capacitor (C1) is connected to the gate of the second transistor (T2), and the other terminal thereof is connected to the second electrode of the second transistor (T2); one terminal of a parasitic capacitor (C2) formed by the light emitting device is connected to the first terminal of the light emitting device (L), and the other terminal thereof is connected to a second terminal of the light emitting device (L); and the second terminal of the light emitting device (L) is further connected to a second power supply signal terminal (ELVSS). The pixel circuit can compensate for the threshold voltage drift of TFT effectively and rise display effect.

公开(公告)号：US09620061B2

公开(公告)日：2017-04-11

申请号：US14415701

申请日：2014-04-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao ,  Zhongyuan Wu ,  Liye Duan

IPC: G09G3/32 ,  G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2300/0866 ,  G09G2310/0262 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/043

Abstract: The gate driver circuit is connected to a row of pixel units, each pixel unit includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module being connected to a gate scanning signal, and the driving module being connected to a driving control signal and a driving voltage. The gate driver circuit includes a row pixel controlling unit configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor; and a driving control unit configured to provide the driving control signal to the driving module so as to control the driving module to drive the light-emitting device.

公开(公告)号：US20140160416A1

公开(公告)日：2014-06-12

申请号：US14096798

申请日：2013-12-04

Applicant: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. ,  Boe Technology Group Co., Ltd.

Inventor： Xiao Wang ,  Kun Cao

IPC: G02F1/1343

CPC classification number: G02F1/13624 ,  G02F1/134363 ,  G02F2001/133397

Abstract: An array substrate, a method of manufacturing the same, and a display device are provided to effectively eliminate the afterimage phenomenon and improve the display quality of display device. A pixel electrode, a common electrode, a first TFT and a second TFT are provided in a sub-pixel region defined by Nth and (N+1)th gate lines of a plurality of gate lines and two data lines of the plurality of data lines, and a multi-dimensional electric field is formed when the pixel electrode and the common electrode are powered. A first gate electrode of the first TFT is connected to the (N+1)th gate line, a first source electrode of a first TFT is connected to one of the two data lines, a first drain electrode of the first TFT is connected to the pixel electrode; a second gate electrode of a second TFT is connected to the Nth gate line, a second drain electrode of the second TFT is connected to the pixel electrode, a second source electrode of the second TFT is connected to the common electrode; and the Nth gate line comprises any one of the plurality of gate lines except the last one, and during a gate line scanning process for one frame in the array substrate, the Nth gate line is always scanned in advance of the (N+1)th gate line.

Abstract translation: 提供阵列基板，其制造方法和显示装置，以有效地消除残像现象并提高显示装置的显示质量。 像素电极，公共电极，第一TFT和第二TFT设置在由多条栅极线的第N条和第（N + 1）条栅极线和多个数据中的两条数据线限定的子像素区域中 并且当像素电极和公共电极被供电时形成多维电场。 第一TFT的第一栅电极连接到第（N + 1）栅极线，第一TFT的第一源电极连接到两条数据线之一，第一TFT的第一漏电极连接到 像素电极; 第二TFT的第二栅电极连接到第N栅极线，第二TFT的第二漏电极连接到像素电极，第二TFT的第二源电极连接到公共电极; 并且第N栅极线包括除了最后一个之外的多个栅极线中的任何一个，并且在阵列基板中的一个帧的栅极线扫描处理期间，第N个栅极线总是在（N + 1） 门闸线。

公开(公告)号：US10459299B2

公开(公告)日：2019-10-29

申请号：US15239100

申请日：2016-08-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  H01L27/02 ,  H01L27/12

Abstract: An electro-static discharge (ESD) protection unit, an array substrate, a liquid crystal display panel and a display device. The ESD protection unit includes: a thin-film transistor (TFT); a first trace; and a second trace. A gate electrode of the TFT is exposed in a region that is formed by the first trace and the second trace and corresponds to a pixel unit, and the gate electrode of the TFT is configured to collect electric charges generated between the first trace and the second trace. A source electrode of the TFT is connected to the first trace and a drain electrode of the TFT is connected to the second trace.

公开(公告)号：US09966041B2

公开(公告)日：2018-05-08

申请号：US14787893

申请日：2015-04-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao ,  Zhongyuan Wu ,  Chen Song

IPC: G09G5/10 ,  G09G3/3266 ,  G11C19/28

Abstract: A display circuit and a driving method thereof and a display apparatus are provided. The display circuit comprises a pixel unit (11), a first gate driving unit (12) and a second gate driving unit (13); wherein the first gate driving unit (12) is configured to input a first gate driving signal to the pixel unit (11); the second gate driving unit (13) is configured to input a second gate driving signal to the pixel unit (11); and the pixel unit (11) is configured to perform threshold compensating and gray scale displaying simultaneously under the control of the first gate driving signal and the second gate driving signal. The apparatus and method is capable of reducing the complexity in design of the display circuit, which is advantageous for raising density of pixels of the display panel. The apparatus and method are applicable to manufacture a display.

公开(公告)号：US09865211B2

公开(公告)日：2018-01-09

申请号：US14416884

申请日：2014-04-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

Abstract: There are provided a shift register unit, a gate driving circuit and a display device, which enable gate lines in non-output rows to remain in the state of no signal outputting. The shift register unit comprises an input module (10), a pull-up module (20), a pull-down control module (30), a first pull-down module (31), a second pull-down module (40) and a reset module (50). In the non-output time, the first pull-down module and the second pull-down module pull down the output voltages of the pull-up modules connected thereto to a low level alternately, thereby enabling gate lines in non-output rows to remain in the state of no signal outputting.

公开(公告)号：US09831297B2

公开(公告)日：2017-11-28

申请号：US15121960

申请日：2015-11-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao

IPC: H01L27/32 ,  H01L51/52 ,  H01L51/56

CPC classification number: H01L27/3279 ,  H01L27/32 ,  H01L27/3246 ,  H01L27/3258 ,  H01L51/52 ,  H01L51/5212 ,  H01L51/5228 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/5315

Abstract: The present invention relates to an AMOLED array substrate, a manufacturing method thereof and a display device. The AMOLED array substrate includes at least one first auxiliary line provided in the same layer as but not intersecting with pixel electrodes; and at least one second auxiliary line provided in the same layer as source and drain electrodes but not intersecting with data lines and the source and drain electrodes, wherein: projections of the first and second auxiliary lines on plate electrode are within projection of pixel define layer and at least partially overlap; and the first auxiliary line is electrically connected to the second auxiliary line via a first via hole and to the plate electrode via a second via hole formed in pixel define layer, wherein projection of the first via hole on the plate electrode is within overlapped projection of the first and second auxiliary lines.