公开(公告)号：US20160013318A1

公开(公告)日：2016-01-14

申请号：US14436309

申请日：2014-07-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang LIU ,  Woobong LEE

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02658 ,  H01L29/66969

Abstract: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an insulating layer and a metal oxide semiconductor layer which are adjacent to each other, and the insulating layer is formed by steps of: forming a first silicon oxide film; and stabilizing the first silicon oxide film by filling a silicon dangling bond therein with a filling atom capable of being bonded to the silicon dangling bond.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括彼此相邻的绝缘层和金属氧化物半导体层，并且绝缘层通过以下步骤形成：形成第一氧化硅膜; 以及通过用能够与硅悬挂键结合的填充原子填充硅悬挂键来稳定第一氧化硅膜。

公开(公告)号：US20240219789A1

公开(公告)日：2024-07-04

申请号：US17918647

申请日：2021-11-30

Applicant: Wuhan BOE Optoelectronics Technology Co.,Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Yiyi ZHANG ,  Wei WU ,  Yan CHEN ,  Dang ZHANG ,  Junfeng DAI ,  Xiang LIU ,  Yichen ZHOU ,  Hao ZHANG ,  Mingyu XIAO ,  Zizheng LIU ,  Yuan TONG ,  Qi CHEN ,  Taohe ZHU

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1345

CPC classification number: G02F1/136286 ,  G02F1/134363 ,  G02F1/13452

Abstract: Embodiments of the present disclosure provide a display substrate having a display region and a frame region. The display substrate includes a plurality of display pixels and a plurality of dummy pixels arranged in an array; the display pixels are distributed in the display region; the dummy pixels are distributed in the frame region. Each display pixel includes a first pixel electrode and a first common electrode; and a first voltage difference exists between the first pixel electrode and the first common electrode. Each dummy pixel includes a second pixel electrode and a second common electrode; and a second voltage difference exists between the second pixel electrode and the second common electrode. A difference between the first voltage difference and the second voltage difference is less than a set value. Embodiments of the present disclosure further provides a display panel and a display apparatus.

公开(公告)号：US20220178013A1

公开(公告)日：2022-06-09

申请号：US17680478

申请日：2022-02-25

Applicant: Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jinbiao LIU ,  Luoyang FENG ,  Youliang LI ,  Tianyu XU ,  Rui TAN ,  Yongyong WEI ,  Xiang LIU ,  Li CHEN ,  Kai WEN ,  Qinwen JIANG ,  Shangshu SUN ,  Peng LIU

IPC: C23C14/24 ,  C23C14/12 ,  H01L51/56

Abstract: An evaporation source includes a crucible, a heater, a heat adjusting assembly for convecting heat radiation between the heat adjusting assembly and the crucible body and including a first reflection plate and a second reflection plate, and a hollowed-out pattern provided in the second reflection plate. The crucible includes a crucible body having a top surface, a bottom surface and side surfaces connecting the top and the bottom surfaces; and a nozzle disposed on the top surface of the crucible body. The heater is disposed outside the crucible body for generating heat radiation. Wherein the first reflection is disposed on at least one side of the side surfaces of the crucible body, a gap exists between the first reflection plate and the crucible body; the second reflection plate is disposed under the bottom surface of the crucible body, a gap exists between the second reflection plate and the crucible body.

公开(公告)号：US20180242412A1

公开(公告)日：2018-08-23

申请号：US15548521

申请日：2017-01-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE DISPLAY LIGHTING CO., LTD.

Inventor： Yaling KANG ,  Xiaochu ZHANG ,  Zuchuan SHI ,  Shuyong HE ,  Bo WU ,  Xiang LIU ,  Peina WANG

IPC: H05B33/08 ,  H04N13/20 ,  F21V8/00 ,  F21S4/28

CPC classification number: H05B33/0803 ,  F21S4/28 ,  G02B6/0011 ,  G02B6/0068 ,  G02B6/009

Abstract: A back plate, a backlight module, a display device, and an assembly method of the backlight module are provided. The backlight module includes: a back plate, including a main body portion, the main body portion having a first main surface and a second main surface opposite to each other; and the main body portion being provided with a hollow structure; a light source, passing through the hollow structure from a second main surface side of the main body portion; a light guide plate, provided on the first main surface side of the main body portion of the back plate, wherein, the light-emitting portion of the light source includes a light emergent surface, and the light emergent surface faces a light incident surface of the light guide plate.

公开(公告)号：US20160336453A1

公开(公告)日：2016-11-17

申请号：US15098398

申请日：2016-04-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang LIU

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696

Abstract: An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode. A length of a shortest distance on the semiconductor layer from the first connection point to the second connection point may be no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode.

Abstract translation: 根据本公开提供的阵列基板可以包括：基底; 依次形成在所述基底基板上的栅极电极和栅极绝缘层; 形成在已经形成有栅极绝缘层的基底基板上的半导体层; 以及形成在已经形成有半导体层的基底基板上的源电极和漏电极。 半导体层可以分别连接到源电极和漏电极。 第一连接点所在的第一连接区域可以布置在半导体层和源电极之间。 并且其中第二连接点所在的第二连接区域可以布置在半导体层和漏电极之间。 从第一连接点到第二连接点的半导体层上的最短距离的长度可以不小于参考距离，该参考距离是指在距离第二连接点的周长上的所有点中的任何两点之间的直线的最长距离 栅电极。

公开(公告)号：US20160020103A1

公开(公告)日：2016-01-21

申请号：US14362423

申请日：2013-12-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang LIU

IPC: H01L21/283 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L21/283 ,  H01L21/76841 ,  H01L21/76856 ,  H01L23/53238 ,  H01L27/1214 ,  H01L29/45 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A barrier layer, a method for fabricating the same, a thin film transistor (TFT) and an array substrate are disclosed and related to display technology field. When the barrier layer (40) is applied to a TFT, it can block Cu atoms from diffusing to other layers, thereby reducing the harm to the performance of the TFT. The barrier layer (40) comprises at least two layers (401, 402) of conductive films; grain boundaries (70) in any layer (401, 402) of the conductive films are arranged in a staggered manner relative to grain boundaries (70) in another layer (401, 402) of the conductive films contacting therewith.

Abstract translation: 公开了一种阻挡层及其制造方法，薄膜晶体管（TFT）和阵列基板，涉及显示技术领域。 当阻挡层（40）施加到TFT时，它可以阻止Cu原子扩散到其它层，从而减少对TFT性能的损害。 阻挡层（40）包括导电膜的至少两层（401,402）; 导电膜的任何层（401,402）中的晶界（70）在与其接触的导电膜的另一层（401,402）中以相互相对于晶界（70）的交错方式布置。

公开(公告)号：US20140168556A1

公开(公告)日：2014-06-19

申请号：US14105600

申请日：2013-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang LIU

IPC: G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: The example of present invention provides an array substrate, the method for manufacturing the same, and a liquid crystal display device, wherein the array substrate comprises: a gate electrode, a gate insulating layer, a barrier layer pattern and an active semiconductor layer pattern formed by metal oxide semiconductor which are located on the gate insulating layer, a semiconductor protecting layer which covers the barrier layer pattern and the active semiconductor layer pattern, and has via holes at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern; a data wire, a source electrode and a drain electrode formed by metal Cu, which are located at via holes. Metal Cu is used to form the data wire, the source electrode and the drain electrode, and the metal oxide semiconductor is used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu into the layers such as the gate insulating layer etc., is prevented in the manufacturing process of TFT.

Abstract translation: 本发明的实例提供阵列基板，其制造方法和液晶显示装置，其中阵列基板包括：栅电极，栅极绝缘层，阻挡层图案和形成的有源半导体层图案 通过位于栅极绝缘层上的金属氧化物半导体，覆盖阻挡层图案和有源半导体层图案的半导体保护层，并且在对应于阻挡层图案和有源半导体层图案的位置具有通孔; 由金属Cu形成的数据线，源电极和漏极，位于通孔处。 使用金属Cu形成数据线，源电极和漏电极，并且使用金属氧化物半导体作为金属Cu的阻挡层，结果，金属Cu扩散到诸如 栅极绝缘层等在TFT的制造工艺中被防止。

公开(公告)号：US20240272493A1

公开(公告)日：2024-08-15

申请号：US18042522

申请日：2022-06-29

Applicant: BOE Technology Group Co., Ltd. ,  Wuhan BOE Optoelectronics Technology Co., Ltd.

Inventor： Qi CHEN ,  Yujie GAO ,  Wei WU ,  Hao ZHANG ,  Yuan TONG ,  Yichen ZHOU ,  Dang ZHANG ,  Yiyi ZHANG ,  Xiang LIU ,  Taohe ZHU ,  Junfeng DAI ,  Jinli LI ,  Bo HUANG

IPC: G02F1/1343 ,  G02F1/1337

CPC classification number: G02F1/134336 ,  G02F1/13378 ,  G02F1/13439

Abstract: The present disclosure provides a display substrate, a manufacturing method of the display substrate and a display apparatus. The display substrate includes a base substrate; an alignment layer, on the base substrate; a first electrode, located between the base substrate and the alignment layer and being in contact with the alignment layer; and a pattern layer, located between the base substrate and the alignment layer and being in contact with the alignment layer. An orthographic projection of the pattern layer on the base substrate does not overlap an orthographic projection of the first electrode on the base substrate, and a ratio of a contact angle of the pattern layer to a contact angle of the first electrode is greater than or equal to 7/12 and less than 3/2.

公开(公告)号：US20160268440A1

公开(公告)日：2016-09-15

申请号：US14408493

申请日：2014-05-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang LIU

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78606 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2029/42388

Abstract: The disclosure discloses a thin film transistor and a fabrication method thereof, an array substrate and a display device. The thin film transistor comprises an active layer and an insulating layer adjacent to the active layer. The insulating layer comprises a first insulating layer, the first insulating layer comprises a first silicon oxide film and a second silicon oxide film, and the second silicon oxide film is in direct contact with the active layer. A density of the second silicon oxide film is larger than that of the first silicon oxide film.

Abstract translation: 本公开公开了一种薄膜晶体管及其制造方法，阵列基板和显示装置。 薄膜晶体管包括有源层和与有源层相邻的绝缘层。 绝缘层包括第一绝缘层，第一绝缘层包括第一氧化硅膜和第二氧化硅膜，并且第二氧化硅膜与有源层直接接触。 第二氧化硅膜的密度大于第一氧化硅膜的密度。

公开(公告)号：US20160033800A1

公开(公告)日：2016-02-04

申请号：US14420737

申请日：2014-03-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang LIU

IPC: G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  H01L29/16 ,  H01L29/423 ,  G02F1/1362 ,  H01L29/24

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a thin film transistor, an array substrate and a display device, relating to the field of display technology, for solving the problem that a source/drain electrode metals and a gate metal may be short-circuited in the manufacturing process of an existing bottom-gate thin film transistor. The thin film transistor of the present invention comprises: a gate formed on a substrate, the gate being connected with a gate line; and a semiconductor layer formed on the gate and the gate line, at least a part of the semiconductor layer extends in the direction parallel to the substrate to exceed the edge of the gate. The array substrate of the present invention comprises the thin film transistor, and the display device comprises the array substrate. The present invention may improve the yield of the bottom-gate thin film transistor.

Abstract translation: 本发明提供一种与显示技术领域相关的薄膜晶体管，阵列基板和显示装置，用于解决源极/漏极金属和栅极金属在制造过程中可能短路的问题 现有的底栅薄膜晶体管。 本发明的薄膜晶体管包括：形成在基板上的栅极，栅极与栅极线连接; 以及形成在栅极和栅极线上的半导体层，半导体层的至少一部分在平行于衬底的方向上延伸超过栅极的边缘。 本发明的阵列基板包括薄膜晶体管，显示装置包括阵列基板。 本发明可以提高底栅薄膜晶体管的产量。