公开(公告)号：US10197877B2

公开(公告)日：2019-02-05

申请号：US15504083

申请日：2016-09-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yucheng Chan ,  Shuai Zhang

IPC: G02F1/13 ,  G02F1/1362 ,  H01L21/77 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1368

Abstract: An array substrate includes multiple pattern layers disposed in a display region and a test unit disposed in a non-display region, the test unit includes at least one of a test component and a test transistor. The test component includes a test block pattern and a test line pattern; the test block pattern is disposed in the same layer as one layer of the multiple pattern layers, the test line pattern is disposed in the same layer as one layer of the multiple pattern layers, and the test block pattern and the test line pattern are disposed in different layers; the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate; and the test block pattern or the test line pattern is connected to the test transistor.

公开(公告)号：US10061173B2

公开(公告)日：2018-08-28

申请号：US15305334

申请日：2015-09-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shuai Zhang ,  Yu Cheng Chan

IPC: H01L29/04 ,  G02F1/1368 ,  G02F1/1343 ,  H01L51/05 ,  H01L51/10 ,  H01L27/28 ,  H01L21/02 ,  H01L21/3105

CPC classification number: G02F1/1368 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  C08K3/041 ,  G02F1/134309 ,  G02F1/13439 ,  G02F2001/136295 ,  G02F2001/13685 ,  G02F2202/36 ,  H01L21/02274 ,  H01L21/31053 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/057 ,  H01L51/0591 ,  H01L51/105

Abstract: Various embodiments provide a thin film transistor (TFT), a fabrication method thereof, and a display apparatus including the TFT. A carbon nanotube layer is formed over a substrate. The carbon nanotube layer includes a first plurality of carbon nanotubes. A plurality of gaps are formed through the carbon nanotube layer to provide a first patterned carbon nanotube layer. Carbon nanotube structures each including a second plurality of carbon nanotubes are formed in the plurality of gaps. The carbon nanotube structures have a carrier mobility different from the first patterned carbon nanotube layer, thereby forming an active layer for forming active structures of the thin-film transistor.

公开(公告)号：US09893131B2

公开(公告)日：2018-02-13

申请号：US15513290

申请日：2016-10-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yucheng Chan ,  Shuai Zhang

IPC: H01L27/32 ,  H01L25/03 ,  H01L21/66 ,  H01L27/24 ,  G02F1/1362

CPC classification number: H01L27/3248 ,  G02F1/1362 ,  G02F2001/136254 ,  H01L22/30 ,  H01L25/03 ,  H01L27/2481

Abstract: The present application discloses an array substrate having a plurality of semiconductor elements and a plurality of test electrodes. Each of the plurality of semiconductor elements comprises a plurality of terminals, each of which is electrically connected to a different test electrode. At least one of the plurality of test electrodes is electrically connected to at least two different semiconductor elements.

公开(公告)号：US11348356B2

公开(公告)日：2022-05-31

申请号：US16521077

申请日：2019-07-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yucheng Chan ,  Shuai Zhang

IPC: G06F3/041 ,  G06V40/13 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

Abstract: The present disclosure provides a display substrate which includes: a base substrate; a light emitting layer located on the base substrate, the light emitting layer including light emitting regions and non-light emitting regions which are arranged alternately, the light emitting regions including multiple light emitting units; and the display substrate further includes a fingerprint recognition region including a touch layer which is disposed on a side of the light emitting layer distal to the base substrate and corresponds to the non-light emitting regions of the light emitting layer, the touch layer including an opaque pattern; the touch layer is provided with at least one pinhole.

公开(公告)号：US20220157919A1

公开(公告)日：2022-05-19

申请号：US17589810

申请日：2022-01-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Hongwei Tian ,  Yanan Niu ,  Chunyang Wang ,  Dong Li ,  Zheng Liu ,  Shuai Zhang

IPC: H01L27/32 ,  G09G3/3266 ,  H01L51/52

Abstract: A display substrate having a display area and a gate-on-array (GOA) area outside the display area is provided. The display substrate includes a base substrate; a plurality of GOA signal lines on the base substrate and in the GOA area; and a first signal line in the GOA area, at least a portion of the first signal line being on a side of the plurality of GOA signal lines away from the base substrate. An orthographic projection of the first signal line on the base substrate at least partially covers an orthographic projection of at least one of a first clock signal line, a second clock signal line, a start signal line, a high voltage power line, or a low voltage power line on the base substrate.

公开(公告)号：US11222586B2

公开(公告)日：2022-01-11

申请号：US16632169

申请日：2019-05-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dong Li ,  Hongwei Tian ,  Xiaolong Li ,  Shuai Zhang ,  Chunyang Wang

IPC: G09G3/3266 ,  G09G3/3233 ,  H01L27/32 ,  H01L51/00 ,  H01L51/56 ,  G09G3/3275

Abstract: A display panel is disclosed. The display panel includes a flexible substrate; a display sub-region on the flexible substrate including a light emitting device; a peripheral region of the display sub-region spacing the display sub-region from an adjacent display sub-region; and a current compensator in the peripheral region for compensating a current flowing through the light emitting device of the display sub-region in response to deformation of the flexible substrate.

公开(公告)号：US10998385B2

公开(公告)日：2021-05-04

申请号：US16399156

申请日：2019-04-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yueping Zuo ,  Shuai Zhang ,  Shantao Chen

IPC: H01L27/32 ,  H01L51/52 ,  G06K9/00 ,  H01L51/56

Abstract: A display element, a method for fabricating the same, and a display device are provided. The display element includes: a blocking layer; a fingerprint sensor on one side of the blocking layer; a light-shielding layer on the side of the blocking layer away from the fingerprint sensor, wherein the light-shielding layer includes a first via-hole; a middle layer on the light-shielding layer; a pixel definition layer on the middle layer, wherein the pixel definition layer includes a second via-hole in which a cathode layer and a light-emitting layer are arranged; an antireflection coating on the pixel definition layer; and an anode layer on the light-emitting layer.

公开(公告)号：US20200027903A1

公开(公告)日：2020-01-23

申请号：US16509548

申请日：2019-07-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xueyan Tian ,  Zheng Liu ,  Shuai Zhang

IPC: H01L27/12

Abstract: The present disclosure discloses an array substrate, a manufacturing method thereof, a display substrate, and a display device, belonging to the technical field of display. The array substrate includes: a flexible base, and, a TFT and a connecting line which are on a side of the flexible base. The array substrate has a display area and a lead area. The TFT is in the display area. The connecting line is in the lead area. The connecting line is used to electrically connect the TFT to a drive circuit. A manufacturing material of the connecting line includes a flexible conductive material. Since the material forming the connecting line includes a flexible conductive material, and the flexible conductive material has electrical conductivity and is not easily broken, the breaking probability of the connecting line is reduced, and the yield of the display device is effectively improved.

公开(公告)号：US10355022B2

公开(公告)日：2019-07-16

申请号：US15393030

申请日：2016-12-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jian Min ,  Xiaolong Li ,  Zhengyin Xu ,  Tao Gao ,  Dong Li ,  Shuai Zhang

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/00 ,  H01L29/786

Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer on a substrate, wherein source-and-drain-to-be-formed regions of the active layer are thicker than a semiconductor region between the source-and-drain-to-be-formed regions, and by a patterning process, forming a gate on the active layer, and forming a pattern of source and drain in the source-and-drain-to-be-formed regions of the active layer.

公开(公告)号：US20180107080A1

公开(公告)日：2018-04-19

申请号：US15504083

申请日：2016-09-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yucheng Chan ,  Shuai Zhang

IPC: G02F1/1362 ,  G02F1/1343 ,  H01L27/12 ,  G02F1/13 ,  G02F1/1368 ,  H01L21/77

CPC classification number: G02F1/136286 ,  G02F1/1309 ,  G02F1/134363 ,  G02F1/1368 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124

Abstract: An array substrate, includes multiple pattern layers disposed in a display region and a test unit disposed in a non-display region, the test unit includes at least one of a test component and a test transistor. The test component includes a test block pattern and a test line pattern; the test block pattern is disposed in the same layer as one layer of the multiple pattern layers, the test line pattern is disposed in the same layer as one layer of the multiple pattern layers, and the test block pattern and the test line pattern are disposed in different layers; the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate; and the test block pattern or the test line pattern is connected to the test transistor.