-
公开(公告)号：US11650754B2
公开(公告)日：2023-05-16
申请号：US16689479
申请日：2019-11-20
Inventor： Zihao Liang , Jian Ouyang
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0653 , G06F3/0656 , G06F3/0683
Abstract: Embodiments of the present disclosure provide a data accessing method, a device and a storage medium. The method includes: obtaining a first accessing request and a second accessing request for a storage device; loading first data associated with the first accessing request from a source device to a pre-allocated buffer area with a size same as a size of a single physical storage block of the storage device; determining a first part of the second data when the first size of second data associated with the second accessing request is greater than or equal to the second size of an available space of the buffer area, a size of the first part being the same as the second size; and providing the first data and the first part to a target device associated with the first accessing request and the second accessing request.
-
公开(公告)号：US10951595B2
公开(公告)日：2021-03-16
申请号：US15618655
申请日：2017-06-09
Inventor： Wei Qi , Jian Ouyang , Yong Wang , Yichen Tu , Sijie Yang
Abstract: The present application discloses a method, system and apparatus for storing a website private key plaintext. A specific implementation of the method includes: receiving a public key sent from a terminal configured to perform encryption and decryption, wherein the public key is generated at random by the terminal; encrypting a website private key plaintext by using the public key to generate a website private key ciphertext, wherein the website private key plaintext is pre-acquired; and sending the website private key ciphertext to the terminal, so that the terminal decrypts the website private key ciphertext by using the private key to generate the website private key plaintext and store the website private key plaintext in the terminal. This implementation improves the security of storage of the website private key plaintext.
-
公开(公告)号：US20200050456A1
公开(公告)日：2020-02-13
申请号：US16502628
申请日：2019-07-03
Inventor： Jian Ouyang
Abstract: Embodiments of the present disclosure relate to a method for processing information, and a processor. The processor includes an arithmetic and logic unit, a bypass unit, a queue unit, a multiplexer, and a register file. The bypass unit includes a data processing subunit; the data processing subunit is configured to acquire at least one valid processing result outputted by the arithmetic and logic unit, determine a processing result from the at least one valid processing result, output the determined processing result to the multiplexer, and output processing results except for the determined processing result of among the at least one valid processing result to the queue unit; and the multiplexer is configured to sequentially output more than one valid processing results to the register file.
-
公开(公告)号：US20190164254A1
公开(公告)日：2019-05-30
申请号：US16265566
申请日：2019-02-01
Inventor： Yichen Tu , Jian Ouyang , Wei Qi , Yong Wang
Abstract: A processor and method for scaling an image are disclosed. A specific embodiment of the processor includes: an off-chip memory, a communication circuit, a control circuit, and an array processor, wherein: the off-chip memory is configured for storing a to-be-scaled original image; the communication circuit is configured for receiving an image scaling instruction; the control circuit is configured for executing the image scaling instruction, and sending a calculation control signal to the array processor; and the array processor is configured for calculating in parallel channel values of N channels in a target pixel using N processing elements in the array processor under the control of the calculation control signal based on a width scaling factor, a height scaling factor, and channel values of N channels in extracted pixel data. The embodiment has improved the processing speed of an image scaling operation.
-
15.发明授权公开(公告)号：US11485376B2
公开(公告)日：2022-11-01
申请号：US16711187
申请日：2019-12-11
Inventor： Chongqin Wang , Zhibiao Zhao , Hefei Zhu , Ningyi Xu , Jian Ouyang
IPC: B60W50/04 , B60W50/02 , B60W50/035
Abstract: An automatic processing system, a system on chip and a method for monitoring a processing module are described herein. The automatic driving processing system comprises: an automatic driving processing module, configured for receiving an input data stream and processing the input data stream based on a deep learning model so as to generate a processing result; a fault detection module, configured for generating a control signal and a fault detection stimulating data stream, and receiving the processing result from the automatic driving processing module; and a multi-way selection module, configured for receiving an automatic driving data stream as well as the control signal and the fault detection stimulating data stream, and selectively outputting the automatic driving data stream or the fault detection stimulating data stream to the automatic driving processing module based on the control signal, as an input data stream.
-
Patent Agency Ranking
公开(公告)号：US20210241095A1
公开(公告)日：2021-08-05
申请号：US17017600
申请日：2020-09-10
Inventor： Xiaozhang Gong , Jian Ouyang , Jing Wang , Wei Qi
Abstract: Embodiments of the present disclosure propose a deep learning processing apparatus and method, device and storage medium, relating to the field of artificial intelligence. A deep learning processing apparatus includes: at least one matrix multiply-add module, configured to perform a matrix multiply-add operation of a convolution kernel parameter value matrix of a convolutional layer in a convolutional neural network and a first error gradient value matrix to obtain a plurality of intermediate matrices; a storage apparatus, configured to store the plurality of intermediate matrices without reshaping elements in the plurality of intermediate matrices; and a plurality of matrix accumulation modules, configured to read the plurality of intermediate matrices from the storage apparatus and perform a matrix accumulation operation based on the plurality of intermediate matrices according to a convolution scheme of the convolutional layer in parallel, to obtain a second error gradient value matrix for the convolutional layer.
-
公开(公告)号：US10922785B2
公开(公告)日：2021-02-16
申请号：US16265566
申请日：2019-02-01
Inventor： Yichen Tu , Jian Ouyang , Wei Qi , Yong Wang
Abstract: A processor and method for scaling an image are disclosed. A specific embodiment of the processor includes: an off-chip memory, a communication circuit, a control circuit, and an array processor, wherein: the off-chip memory is configured for storing a to-be-scaled original image; the communication circuit is configured for receiving an image scaling instruction; the control circuit is configured for executing the image scaling instruction, and sending a calculation control signal to the array processor; and the array processor is configured for calculating in parallel channel values of N channels in a target pixel using N processing elements in the array processor under the control of the calculation control signal based on a width scaling factor, a height scaling factor, and channel values of N channels in extracted pixel data. The embodiment has improved the processing speed of an image scaling operation.
-
公开(公告)号：US20210034900A1
公开(公告)日：2021-02-04
申请号：US16807775
申请日：2020-03-03
Inventor： Zihao Liang , Jian Ouyang
Abstract: Embodiments of the present disclosure provide a method and apparatus for extracting image data in parallel from multiple convolution windows, a device, and a computer-readable storage medium. The method includes: dividing an image into multiple groups of convolution windows, where the multiple groups of convolution windows include a first group of convolution windows and a second group of convolution windows, and each group of convolution windows include multiple convolution windows. The method further includes extracting image data in parallel from multiple convolution windows in the first group of convolution windows by using multiple data processing units, and extracting, after the extraction of image data from the first group of convolution windows is completed, image data from multiple convolution windows in the second group of convolution windows in parallel by using the multiple data processing units.
-
19.发明申请公开(公告)号：US20200050481A1
公开(公告)日：2020-02-13
申请号：US16506099
申请日：2019-07-09
Inventor： Jian Ouyang , Xueliang Du , Yingnan Xu , Huimin Li
Abstract: Disclosed are a computing method applied to an artificial intelligence chip and the artificial intelligence chip. The method includes: a target processor core generating, in response to determining a computational identifier obtained by decoding a to-be-executed instruction being a preset complex computational identifier, a complex computational instruction using the computational identifier and at least one operand obtained by decoding, and adding the generated complex computational instruction to a complex computational instruction queue; and a computational accelerator selecting a complex computational instruction from the complex computational instruction queue, executing a complex computation indicated by the complex computational identifier in the selected complex computational instruction using the at least one operand in the selected complex computational instruction as an inputted parameter, to obtain computational result; and writing the obtained computational result as a complex computational result into a complex computational result queue.
-
20.发明授权公开(公告)号：US10261796B2
公开(公告)日：2019-04-16
申请号：US15360245
申请日：2016-11-23
Inventor： Jian Ouyang , Wei Qi , Yong Wang
Abstract: A processor and a method for executing an instruction on a processor are provided. In the method, a to-be-executed instruction is fetched, the instruction including a source address field, a destination address field, an operation type field, and an operation parameter field; in at least one execution unit, an execution unit controlled by a to-be-generated control signal according to the operation type field is determined, a source address and a destination address of data operated by the execution unit are determined according to the source address field and the destination address field, and a data amount of the data operated by the execution unit controlled by the to-be-generated control signal is determined according to the operation parameter field; the control signal is generated; and the execution unit in the at least one execution unit is controlled by using the control signal.
-
-
-
-
-
-
-
-
-
Search Results
31
records
(took 0.024 seconds)
