公开(公告)号：US10853262B2

公开(公告)日：2020-12-01

申请号：US16342644

申请日：2017-11-29

Applicant: ARM LIMITED

Inventor： Nikos Nikoleris ,  Andreas Lars Sandberg ,  Prakash S. Ramrakhyani ,  Stephan Diestelhorst

IPC: G06F9/26 ,  G06F12/1009 ,  G11C11/408 ,  G06F12/1027 ,  G11C8/06 ,  G11C11/4096

Abstract: Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data; a translation data buffer to store one or more instances of the translation data, comprising: an array of storage locations arranged in rows and columns; a row buffer comprising a plurality of entries and comparison circuitry responsive to a key value dependent upon at least the initial memory address, to compare the key value with information stored in each of at least one key entry and an associated value entry for storing at least a representation of a corresponding output memory address, and to identify which of the at least one key entry, if any, is a matching key entry storing information matching the key value; and output circuitry to output, when there is a matching key entry, at least the representation of the output memory address.

公开(公告)号：US20240345962A1

公开(公告)日：2024-10-17

申请号：US18294668

申请日：2022-07-21

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Ilias Vougioukas

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: There is provided address translation circuitry and a method for performing address translation. The address translation circuitry is responsive to receipt of a first address to perform an address translation between the first address and a second address by performing a predetermined maximum number of sequential lookups. The address translation circuitry is configured to support regular page tables comprising 2N entries and large page tables comprising 2N*M entries. The address translation circuitry is configured to: perform an intermediate lookup to retrieve information indicative of a sequentially next lookup address and page table size information and, when the page table size information indicates that the sequentially next lookup corresponds to one of the large page table and performing the sequentially next lookup would exceed the predetermined maximum number of sequential lookups, suppress subsequent lookups and generate the second address based on the information indicative of the sequentially next lookup address.

公开(公告)号：US20240220395A1

公开(公告)日：2024-07-04

申请号：US18554773

申请日：2022-02-10

Applicant: Arm Limited

Inventor： Parameshwarappa Anand Kumar Savanth ,  Sahan Sajeewa Hiniduma Udugama Gamage ,  Wei Wang ,  Andreas Lars Sandberg

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3656

Abstract: An apparatus and method are described for generating debug information. The apparatus has processing circuitry for executing a sequence of instructions that includes a plurality of debug information triggering instructions, and debug information generating circuitry for coupling to a debug port. On executing a given debug information triggering instruction, the processing circuitry is arranged to trigger the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction. The generated debug information signal is output from the debug port for reference by a debugger. The control parameter is such that the form of the debug information signal enables the debugger to determine a state of the processing circuitry when the given debug information triggering instruction was executed.

公开(公告)号：US11960945B2

公开(公告)日：2024-04-16

申请号：US17225674

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Andreas Lars Sandberg ,  Roxana Rusitoru

IPC: G06F9/46 ,  G06F9/54 ,  G06F12/02 ,  G06F12/1009 ,  G06F15/78

CPC classification number: G06F9/546 ,  G06F9/542 ,  G06F12/023 ,  G06F12/1009 ,  G06F15/7817

Abstract: Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.

公开(公告)号：US20240078323A1

公开(公告)日：2024-03-07

申请号：US18446528

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Alexander Klimov ,  Andreas Lars Sandberg ,  Roberto Avanzi

IPC: G06F21/60 ,  G06F21/74

CPC classification number: G06F21/602 ,  G06F21/74

Abstract: An apparatus comprises counter tree circuitry configured to store, in a first node of a counter tree, a representation of a parent counter value and in a second node of the counter tree, wherein the second node is a child node of the first node, an encrypted representation of two or more counter values. The encryption operation for forming the encrypted representation of the two or more counter values takes as an input the parent counter value. The apparatus also comprises integrity checking circuitry to check the integrity of an item of data retrieved from memory based on a comparison between a stored authentication code and a generated authentication code generated based on the item of data and a decrypted counter value determined from an encrypted representation of a counter value retrieved from the second node, decrypted using a parent counter value retrieved from the first node.

公开(公告)号：US11263133B2

公开(公告)日：2022-03-01

申请号：US16979624

申请日：2019-03-12

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Stephan Diestelhorst ,  Nikos Nikoleris ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Albin Pierrick Tonnerre

IPC: G06F12/0802

Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

公开(公告)号：US11176058B2

公开(公告)日：2021-11-16

申请号：US16749006

申请日：2020-01-22

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Derek Del Miller

IPC: G06F12/14 ,  H04L9/32 ,  H04L9/08 ,  H04L9/30

Abstract: An apparatus comprises memory storage circuitry comprising a plurality of memory storage locations to store data; an interface to receive an address from a requester; decryption circuitry to obtain a decrypted address by decrypting, based on a decryption key, an address received from the requester; and access control circuitry to select, based on the decrypted address obtained by the decryption circuitry, a memory storage location of the memory storage circuitry to be accessed.

公开(公告)号：US10705848B2

公开(公告)日：2020-07-07

申请号：US16018440

申请日：2018-06-26

Applicant: Arm Limited

Inventor： Ilias Vougioukas ,  Stephan Diestelhorst ,  Andreas Lars Sandberg ,  Nikos Nikoleris

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F9/30

Abstract: A TAGE branch predictor has, as its fallback predictor, a perceptron predictor. This provides a branch predictor which reduces the penalty of context switches and branch prediction state flushes.

公开(公告)号：US12248409B2

公开(公告)日：2025-03-11

申请号：US17756877

申请日：2020-11-12

Applicant: Arm Limited

Inventor： Hector Montaner Mas ,  Andreas Lars Sandberg ,  Roberto Avanzi

IPC: G06F12/00 ,  G06F12/0866 ,  G06F12/14

Abstract: An apparatus including memory access circuitry for controlling access to data stored in the non-trusted memory, and memory security circuitry to verify integrity of data stored in the non-trusted memory. The memory security circuitry has authentication code generation circuitry for generating authentication codes to be associated with the data stored in the non-trusted memory, for use when verifying the integrity of the data. The apparatus also has a trusted storage, and the authentication code generation circuitry is arranged to generate different authentication codes, dependent on whether the authentication code is to be stored in the non-trusted memory or the trusted storage.

公开(公告)号：US12010242B2

公开(公告)日：2024-06-11

申请号：US16925723

申请日：2020-07-10

Applicant: Arm Limited

Inventor： Roberto Avanzi ,  Andreas Lars Sandberg ,  Michael Andrew Campbell ,  Matthias Lothar Boettcher ,  Prakash S. Ramrakhyani

IPC: H04L9/32 ,  G06F21/57 ,  G06F21/64 ,  H04W12/06 ,  G06F12/0875 ,  G06F12/14 ,  G06F21/79

CPC classification number: H04L9/3242 ,  G06F21/57 ,  G06F21/64 ,  H04W12/06 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/79

Abstract: To protect the integrity of data stored in a protected area of memory, data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs. The integrity of the first data block is contingent on the verification authentication code matching the retrieved authentication code.