Post exposure processing apparatus
    11.
    发明授权

    公开(公告)号:US09964863B1

    公开(公告)日:2018-05-08

    申请号:US15435007

    申请日:2017-02-16

    CPC classification number: G03F7/70716 G03F7/70725 H01L21/0273

    Abstract: Implementations described herein relate to apparatus for post exposure processing. More specifically, implementations described herein relate to field-guided post exposure process chambers and cool down/development chambers used on process platforms. In one implementation, a plurality of post exposure process chamber and cool/down development chamber pairs are positioned on a process platform in a stacked arrangement and utilize a shared plumbing module. In another implementation, a plurality of post exposure process chamber and cool down/development chambers are positioned on a process platform in a linear arrangement and each of the chambers utilize an individually dedicated plumbing module.

    SELECTIVE ETCH USING MATERIAL MODIFICATION AND RF PULSING

    公开(公告)号:US20180082861A1

    公开(公告)日:2018-03-22

    申请号:US15828112

    申请日:2017-11-30

    Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

    Method and apparatus for thin wafer carrier

    公开(公告)号:US11094573B2

    公开(公告)日:2021-08-17

    申请号:US16198569

    申请日:2018-11-21

    Abstract: Disclosed herein is an electrostatic chuck (ESC) carrier. The ESC carrier may comprise a carrier substrate having a first surface and a second surface opposite the first surface. A first through substrate opening and a second through substrate opening may pass through the carrier substrate from the first surface to the second surface. A first conductor is in the first through substrate opening, and a second conductor is in the second through substrate opening. The ESC carrier may further comprise a first electrode over the first surface of the carrier substrate and electrically coupled to the first conductor, and a second electrode over the first surface of the carrier substrate and electrically coupled to the second conductor. An oxide layer may be formed over the first electrode and the second electrode.

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