公开(公告)号：US20200105321A1

公开(公告)日：2020-04-02

申请号：US16147454

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Yildiz Sinangil ,  Mohamed H. Abu-Rahma

IPC: G11C7/12 ,  G11C11/419 ,  G11C5/06 ,  G11C5/14

Abstract: A system and method for efficiently managing switching power of bit lines. In various embodiments, a first bit line in a memory array is pre-charged in multiple discrete steps, rather than in one continuous step. For a read operation that completed and read a logic low level from a first storage node, the first bit line is pre-charged from a ground reference level to a first power supply voltage. Similarly, a second bit line corresponding to a second storage node storing an inverse voltage level of the first storage node is pre-charged from a larger second power supply voltage to the smaller first power supply voltage. When the first time interval has elapsed, the first and second bit lines are pre-charged from the first power supply voltage to the second power supply voltage during a second time interval. Discrete steps are also used for pre-charging after write operations.

公开(公告)号：US09922699B1

公开(公告)日：2018-03-20

申请号：US15365361

申请日：2016-11-30

Applicant: Apple Inc.

Inventor： Yildiz Sinangil ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Ajay Bhatia

IPC: G11C11/00 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

CPC classification number: G11C11/417 ,  G11C5/147 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply voltage for a memory array which tracks the data retention voltage of the memory array. In one embodiment, multiple diodes are implemented in parallel between a supply voltage and the memory array. The diodes have different sizes and different voltage drops, and the diode which will cause the voltage to drop closest to without going below the data retention voltage is selected for routing the supply voltage to the memory array. Since the data retention voltage for the memory array varies over temperature, the temperature of the system is monitored. Based on changes in the temperature, the system changes which diode is in the circuit path for supplying power to the memory array so as to reduce leakage current for the memory array.

公开(公告)号：US09672902B1

公开(公告)日：2017-06-06

申请号：US15227669

申请日：2016-08-03

Applicant: Apple Inc.

Inventor： Yildiz Sinangil ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka

IPC: G11C11/41 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/413 ,  G11C11/417

Abstract: In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage.