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    Method and apparatus for ensuring real-time snoop latency
    12.
    发明授权
    Method and apparatus for ensuring real-time snoop latency 有权

    公开(公告)号：US10795818B1

    公开(公告)日：2020-10-06

    申请号：US16418811

    申请日：2019-05-21

    Applicant: Apple Inc.

    Inventor： Harshavardhan Kaushikkar ,  Per H. Hammarlund ,  Brian P. Lilly ,  Michael Bekerman ,  James Vash ,  Manu Gulati ,  Benjamin K. Dodge

    IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0817

    Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

    Adjustable Clock and Power Gating Control
    13.
    发明申请
    Adjustable Clock and Power Gating Control 有权

    公开(公告)号：US20250104742A1

    公开(公告)日：2025-03-27

    申请号：US18759357

    申请日：2024-06-28

    Applicant: Apple Inc.

    Inventor： Michael Bekerman ,  Matthew R. Johnson ,  Lior Zimet ,  Rohit K. Gupta

    IPC: G11C5/14 ,  G06F1/08

    Abstract: Adjustable clock and power gating control is facilitated hereby. In aspects, a power management circuit is coupled to a memory controller circuit that is coupled to a memory resource circuit and to a plurality of heterogeneous client circuits configured to access the memory resource circuit via the memory controller circuit. The power management circuit is configured to receive operating parameters associated with the plurality of client circuits and to determine, based on the operating parameters, a threshold power state for the memory resource circuit. Additionally, the power management circuit is configured to initiate a clock gating operation, a power gating operation, or both for the memory resource circuit and to maintain at least the threshold power state for the memory resource circuit by limiting performance of the clock gating operation, the power gating operation, or both for the memory resource circuit. Other aspects and features are also claimed and described.

    Multi-Processor Power Management Circuit
    14.
    发明申请
    Multi-Processor Power Management Circuit 有权

    公开(公告)号：US20250093937A1

    公开(公告)日：2025-03-20

    申请号：US18540798

    申请日：2023-12-14

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  John H. Kelm ,  Michael Bekerman

    IPC: G06F1/3234

    Abstract: A system includes a power management processor that may be configured to monitor operation of one or more circuit blocks in the system, and to determine a particular performance state of a set of performance states for one or more power domains in the system based on the monitored operation. The system further includes a performance management circuit that may be configured to receive, from the power management processor, an indication of the particular performance state. The performance management circuit may further be configured to determine a transition path from a current performance state to the particular performance state that avoids illegal performance state transitions, and to cause a control circuit to transition to the particular performance state using the transition path.

    Power Management Interface for Multiple Software Requestors
    15.
    发明申请
    Power Management Interface for Multiple Software Requestors 有权

    公开(公告)号：US20250093925A1

    公开(公告)日：2025-03-20

    申请号：US18540723

    申请日：2023-12-14

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  John H. Kelm ,  Josh P. de Cesare ,  Karl D. Wulcan ,  Michael Bekerman

    IPC: G06F1/26

    Abstract: An apparatus includes a control circuit, configured to transition a plurality of power domains into selected performance states, and a set of state request registers. A state request register may include fields that are associated with respective power domains. The apparatus may further include circuit blocks configured to store respective state request values into respective state request registers. A given state request value may indicate a requested performance state for at least one of the power domains. In addition, a performance management circuit may be configured to select, using the associated fields in the registers, a particular performance state for at least one of the power domains. The performance management circuit may be further configured to determine a transition path to sequence to the selected performance state, and to cause the control circuit to transition to the selected performance state using the transition path.

    Error detection and recovery when streaming data
    20.
    发明授权
    Error detection and recovery when streaming data 有权

    公开(公告)号：US12111721B2

    公开(公告)日：2024-10-08

    申请号：US18490675

    申请日：2023-10-19

    Applicant: Apple Inc.

    Inventor： Marc A. Schaub ,  Roy G. Moss ,  Michael Bekerman

    IPC: G06F11/07 ,  G06F13/28

    CPC classification number: G06F11/0793 ,  G06F13/28

    Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

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