公开(公告)号：US11757681B1

公开(公告)日：2023-09-12

申请号：US17934891

申请日：2022-09-23

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Haiming Jin ,  Brian S. Leibowitz ,  Sanjeev K. Maheshwari ,  Chintan S. Thakkar

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885

Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.

公开(公告)号：US10521391B1

公开(公告)日：2019-12-31

申请号：US16204252

申请日：2018-11-29

Applicant: Apple Inc.

Inventor： Jafar Savoj ,  Jose A. Tierno ,  Sanjeev K. Maheshwari ,  Brian S. Leibowitz ,  Pradeep R. Trivedi ,  Gin Yee ,  Emerson S. Fang

IPC: G06F13/42 ,  G06F9/52 ,  G06F13/40

Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.