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公开(公告)号：US10241705B2
公开(公告)日：2019-03-26
申请号：US15352693
申请日：2016-11-16
Applicant: Apple Inc.
Inventor： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC: G06F3/06 , G06F12/0802 , G06F12/123 , G06F12/0831 , G06F12/0864 , G06F12/0877 , G06F12/0846 , G06F12/0853
Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
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公开(公告)号：US20170329646A1
公开(公告)日：2017-11-16
申请号：US15668360
申请日：2017-08-03
Applicant: Apple Inc.
Inventor： Robert A. Drebin , James Wang
CPC classification number: G06F9/5077 , G06T1/20 , G06T1/60
Abstract: Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs allows for fine-grained execution control in various embodiments.
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公开(公告)号：US09600909B2
公开(公告)日：2017-03-21
申请号：US14803926
申请日：2015-07-20
Applicant: Apple Inc.
Inventor： James Wang , Abdulkadir U. Diril
IPC: G09G5/02 , G09G5/06 , G09G5/39 , G06T11/00 , G06T1/20 , G06T15/04 , G06T19/00 , G06T11/40 , G06F15/76 , G06F17/30 , H04N1/60 , H04N5/357 , H04N19/40 , G09G5/37
CPC classification number: G06T11/001 , G06T1/60 , G06T15/04 , G09G5/363 , G09G5/393 , G09G2360/121
Abstract: Techniques are disclosed relating to storing processed texture information. In some embodiments, a graphics unit is configured to store graphics textures in multiple different formats. In some embodiments, texture filtering circuitry in the graphics unit is configured to operate on texture information in a particular format, but not configured to operate on texture information in one or more of the plurality of different formats. In some embodiments, graphics circuitry is configured to receive texture information in the multiple different formats and process the information to generate processed texture information in the particular format that the texture filtering circuitry is configured to operate on. In some embodiments, the graphics unit includes a storage element with entries configured to store the processed texture information, and the texture filtering circuitry is configured to access processed texture information in an entry of the storage element as input for multiple different sampling operations.
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公开(公告)号：US09367474B2
公开(公告)日：2016-06-14
申请号：US13915911
申请日：2013-06-12
Applicant: Apple Inc.
Inventor： Shailendra S. Desai , Gurjeet S. Saund , Deniz Balkan , James Wang
IPC: G06F12/0893 , G06F12/08 , G06F12/12
CPC classification number: G06F12/0893 , G06F12/0802 , G06F12/0888 , G06F12/12 , Y02D10/13
Abstract: Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol.
Abstract translation: 用于翻译SoC中不同协议之间的缓存提示的系统和方法。 SoC中的请求代理生成用于事务的第一高速缓存提示，并且第一高速缓存提示符合第一协议。 第一个缓存提示可以设置为第一个协议定义的保留编码值。 在将事务发送到存储器子系统之前，第一高速缓存提示被转换成第二高速缓存提示。 存储器子系统识别符合第二协议的高速缓存提示，并且第二高速缓存提示符合第二协议。
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公开(公告)号：US10776022B2
公开(公告)日：2020-09-15
申请号：US16266320
申请日：2019-02-04
Applicant: Apple Inc.
Inventor： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC: G06F3/06 , G06F12/0802 , G06F12/123 , G06F12/0831 , G06F12/0864 , G06F12/0877 , G06F12/0846 , G06F12/0853
Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
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Patent Agency Ranking
公开(公告)号：US10120728B2
公开(公告)日：2018-11-06
申请号：US15668360
申请日：2017-08-03
Applicant: Apple Inc.
Inventor： Robert A. Drebin , James Wang
Abstract: Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs allows for fine-grained execution control in various embodiments.
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公开(公告)号：US20170244391A1
公开(公告)日：2017-08-24
申请号：US15046926
申请日：2016-02-18
Applicant: Apple Inc.
Inventor： James Wang , Benjiman L. Goodman , Liang-Kai Wang , Robert D. Kenney
CPC classification number: H03K5/00006 , G06F1/3228 , G06F1/324 , G06F1/329 , Y02D10/126 , Y02D10/24 , Y02D50/20
Abstract: A method and apparatus for saving power in integrated circuits is disclosed. An IC includes functional circuit blocks which are not placed into a sleep mode when idle. A power management circuit may monitor the activity levels of the functional circuit blocks not placed into a sleep mode. When the power management circuit detects that an activity level of one of the non-sleep functional circuit blocks is less than a predefined threshold, it reduce the frequency of a clock signal provided thereto by scheduling only one pulse of a clock signal for every N pulses of the full frequency clock signal. The remaining N−1 pulses of the clock signal may be inhibited. If a high priority transaction inbound for the functional circuit block is detected, an inserted pulse of the clock signal may be provided to the functional unit irrespective of when a most recent regular pulse was provided.
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公开(公告)号：US20170024905A1
公开(公告)日：2017-01-26
申请号：US14803926
申请日：2015-07-20
Applicant: Apple Inc.
Inventor： James Wang , Abdulkadir U. Diril
CPC classification number: G06T11/001 , G06T1/60 , G06T15/04 , G09G5/363 , G09G5/393 , G09G2360/121
Abstract: Techniques are disclosed relating to storing processed texture information. In some embodiments, a graphics unit is configured to store graphics textures in multiple different formats. In some embodiments, texture filtering circuitry in the graphics unit is configured to operate on texture information in a particular format, but not configured to operate on texture information in one or more of the plurality of different formats. In some embodiments, graphics circuitry is configured to receive texture information in the multiple different formats and process the information to generate processed texture information in the particular format that the texture filtering circuitry is configured to operate on. In some embodiments, the graphics unit includes a storage element with entries configured to store the processed texture information, and the texture filtering circuitry is configured to access processed texture information in an entry of the storage element as input for multiple different sampling operations.
Abstract translation: 公开了关于存储经处理的纹理信息的技术。 在一些实施例中，图形单元被配置为以多种不同格式存储图形纹理。 在一些实施例中，图形单元中的纹理滤波电路被配置为以特定格式对纹理信息进行操作，但是未配置为以多种不同格式中的一种或多种形式对纹理信息进行操作。 在一些实施例中，图形电路被配置为以多种不同格式接收纹理信息，并处理该信息以生成纹理过滤电路被配置为操作的特定格式的处理纹理信息。 在一些实施例中，图形单元包括具有配置以存储处理的纹理信息的条目的存储元件，并且纹理过滤电路被配置为访问存储元件的条目中的处理的纹理信息作为多个不同采样操作的输入。
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公开(公告)号：US09274953B2
公开(公告)日：2016-03-01
申请号：US14611423
申请日：2015-02-02
Applicant: Apple Inc.
Inventor： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/0638 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0848 , G06F12/0853 , G06F12/0864 , G06F12/0877 , G06F12/125 , G06F2212/1021 , G06F2212/2515 , G06F2212/282 , G06F2212/601 , G06F2212/62 , Y02D10/13
Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
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公开(公告)号：US08977818B2
公开(公告)日：2015-03-10
申请号：US14032405
申请日：2013-09-20
Applicant: Apple Inc.
Inventor： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/0638 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0848 , G06F12/0853 , G06F12/0864 , G06F12/0877 , G06F12/125 , G06F2212/1021 , G06F2212/2515 , G06F2212/282 , G06F2212/601 , G06F2212/62 , Y02D10/13
Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。
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