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公开(公告)号：US09600909B2
公开(公告)日：2017-03-21
申请号：US14803926
申请日：2015-07-20
Applicant: Apple Inc.
Inventor： James Wang , Abdulkadir U. Diril
IPC: G09G5/02 , G09G5/06 , G09G5/39 , G06T11/00 , G06T1/20 , G06T15/04 , G06T19/00 , G06T11/40 , G06F15/76 , G06F17/30 , H04N1/60 , H04N5/357 , H04N19/40 , G09G5/37
CPC classification number: G06T11/001 , G06T1/60 , G06T15/04 , G09G5/363 , G09G5/393 , G09G2360/121
Abstract: Techniques are disclosed relating to storing processed texture information. In some embodiments, a graphics unit is configured to store graphics textures in multiple different formats. In some embodiments, texture filtering circuitry in the graphics unit is configured to operate on texture information in a particular format, but not configured to operate on texture information in one or more of the plurality of different formats. In some embodiments, graphics circuitry is configured to receive texture information in the multiple different formats and process the information to generate processed texture information in the particular format that the texture filtering circuitry is configured to operate on. In some embodiments, the graphics unit includes a storage element with entries configured to store the processed texture information, and the texture filtering circuitry is configured to access processed texture information in an entry of the storage element as input for multiple different sampling operations.
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公开(公告)号：US20160364899A1
公开(公告)日：2016-12-15
申请号：US14735707
申请日：2015-06-10
Applicant: Apple Inc.
Inventor： Abdulkadir U. Diril , Adam T. Moerschell , Anthony P. DeLaurier
CPC classification number: G06T15/04 , G06F3/14 , G06T1/20 , G06T2200/28 , G06T2210/36 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2330/021 , G09G2340/04
Abstract: Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.
Abstract translation: 公开了关于确定图形纹理的指定级别的细节的位置的技术。 在一些实施例中，设备包括纹理处理电路，其被配置为接收指定用于图形纹理的存储mipmap的链中的特定mipmap的信息，并确定特定mipmap的偏移地址。 在这些实施例中，纹理处理电路被配置为通过对指示图形处理元件中的mipmap的链的最大潜在链大小的值进行操作来确定偏移地址。 在这些实施例中，操作包括基于纹理的大小掩蔽该值的高位，并且基于所存储的mipmap中的指定的mipmap的位置来屏蔽该值的较低位。 公开的技术可以减少配置成确定偏移的电路的功率消耗和/或电路的面积。
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Patent Agency Ranking
公开(公告)号：US10255655B1
公开(公告)日：2019-04-09
申请号：US15625723
申请日：2017-06-16
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Abdulkadir U. Diril , Anthony P. Delaurier
Abstract: Techniques relating to serial processing of pixels in a texture processing pipeline. In some embodiments, the pipeline receives pixel data for a set of pixels in parallel but processes the pixels in the set serially in a pipelined fashion. In some embodiments, the pipeline includes a stage configured to retain texel data for use by a subsequently processed pixel. They may allow overlapping texels to be fetched once for the set of pixels rather than multiple times for different pixels in the set. In some embodiments, the pipeline uses a selected ordering of serial processing for the pixels, where the ordering increases the potential for texel overlap, relative to one or more other orderings.
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公开(公告)号：US09761303B2
公开(公告)日：2017-09-12
申请号：US15009200
申请日：2016-01-28
Applicant: Apple Inc.
Inventor： Abdulkadir U. Diril , Adam T. Moerschell , Anthony P. DeLaurier
IPC: G11C11/00 , G11C11/419
CPC classification number: G11C11/419 , G11C7/22 , G11C19/00
Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.
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公开(公告)号：US10354431B2
公开(公告)日：2019-07-16
申请号：US14735707
申请日：2015-06-10
Applicant: Apple Inc.
Inventor： Abdulkadir U. Diril , Adam T. Moerschell , Anthony P. DeLaurier
Abstract: Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.
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公开(公告)号：US20170221550A1
公开(公告)日：2017-08-03
申请号：US15009200
申请日：2016-01-28
Applicant: Apple Inc.
Inventor： Abdulkadir U. Diril , Adam T. Moerschell , Anthony P. DeLaurier
IPC: G11C11/419
CPC classification number: G11C11/419 , G11C7/22 , G11C19/00
Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.
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公开(公告)号：US20170024905A1
公开(公告)日：2017-01-26
申请号：US14803926
申请日：2015-07-20
Applicant: Apple Inc.
Inventor： James Wang , Abdulkadir U. Diril
CPC classification number: G06T11/001 , G06T1/60 , G06T15/04 , G09G5/363 , G09G5/393 , G09G2360/121
Abstract: Techniques are disclosed relating to storing processed texture information. In some embodiments, a graphics unit is configured to store graphics textures in multiple different formats. In some embodiments, texture filtering circuitry in the graphics unit is configured to operate on texture information in a particular format, but not configured to operate on texture information in one or more of the plurality of different formats. In some embodiments, graphics circuitry is configured to receive texture information in the multiple different formats and process the information to generate processed texture information in the particular format that the texture filtering circuitry is configured to operate on. In some embodiments, the graphics unit includes a storage element with entries configured to store the processed texture information, and the texture filtering circuitry is configured to access processed texture information in an entry of the storage element as input for multiple different sampling operations.
Abstract translation: 公开了关于存储经处理的纹理信息的技术。 在一些实施例中，图形单元被配置为以多种不同格式存储图形纹理。 在一些实施例中，图形单元中的纹理滤波电路被配置为以特定格式对纹理信息进行操作，但是未配置为以多种不同格式中的一种或多种形式对纹理信息进行操作。 在一些实施例中，图形电路被配置为以多种不同格式接收纹理信息，并处理该信息以生成纹理过滤电路被配置为操作的特定格式的处理纹理信息。 在一些实施例中，图形单元包括具有配置以存储处理的纹理信息的条目的存储元件，并且纹理过滤电路被配置为访问存储元件的条目中的处理的纹理信息作为多个不同采样操作的输入。
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