公开(公告)号：US20250013576A1

公开(公告)日：2025-01-09

申请号：US18777905

申请日：2024-07-19

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20240111685A1

公开(公告)日：2024-04-04

申请号：US18475890

申请日：2023-09-27

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US11327896B2

公开(公告)日：2022-05-10

申请号：US16908182

申请日：2020-06-22

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20200320013A1

公开(公告)日：2020-10-08

申请号：US16908182

申请日：2020-06-22

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20190095339A1

公开(公告)日：2019-03-28

申请号：US16124166

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F17/16 ,  G11C11/419 ,  G06F12/06

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US09448872B2

公开(公告)日：2016-09-20

申请号：US14179191

申请日：2014-02-12

Applicant: Apple Inc.

Inventor： Ben D. Jarrett ,  Fritz A. Boehm

IPC: G06F17/50 ,  G06F11/07 ,  G01R31/317 ,  G06F11/22

CPC classification number: G06F11/0778 ,  G01R31/31705 ,  G06F11/22 ,  G06F11/3476 ,  G06F17/40

Abstract: Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.

Abstract translation: 利用硬件状态数据记录器在硅中进行调试的系统和方法。 将一个或多个硬件状态数据记录器结合到电路设计中并与电路的功能单元一起制造成制造的芯片。 当在制造的芯片的测试期间遇到问题时，硬件状态数据记录器能够捕获并存储导致错误的最终事件序列。 然后从制造的芯片中提取存储的数据，并用于确定故障的根本原因。