公开(公告)号：US11734490B2

公开(公告)日：2023-08-22

申请号：US17564837

申请日：2021-12-29

Applicant: ASML NETHERLANDS B.V.

Inventor： Quan Zhang ,  Been-Der Chen ,  Rafael C. Howell ,  Jing Su ,  Yi Zou ,  Yen-Wen Lu

IPC: G06F30/30 ,  G03F1/30 ,  G03F7/20 ,  G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G03F7/00 ,  G06F119/18

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70441 ,  G03F7/705 ,  G06F2119/18

Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

公开(公告)号：US11232249B2

公开(公告)日：2022-01-25

申请号：US16976492

申请日：2019-02-28

Applicant: ASML NETHERLANDS B.V.

Inventor： Quan Zhang ,  Been-Der Chen ,  Rafael C. Howell ,  Jing Su ,  Yi Zou ,  Yen-Wen Lu

IPC: G06F30/30 ,  G03F1/30 ,  G03F7/20 ,  G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F119/18

Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

公开(公告)号：US11635699B2

公开(公告)日：2023-04-25

申请号：US17312709

申请日：2019-12-04

Applicant: ASML NETHERLANDS B.V.

Inventor： Youping Zhang ,  Maxime Philippe Frederic Genin ,  Cong Wu ,  Jing Su ,  Weixuan Hu ,  Yi Zou

IPC: G03F7/20

Abstract: Methods for training a process model and determining ranking of simulated patterns (e.g., corresponding to hot spots). A method involves obtaining a training data set including: (i) a simulated pattern associated with a mask pattern to be printed on a substrate, (ii) inspection data of a printed pattern imaged on the substrate using the mask pattern, and (iii) measured values of a parameter of the patterning process applied during imaging of the mask pattern on the substrate; and training a machine learning model for the patterning process based on the training data set to predict a difference in a characteristic of the simulated pattern and the printed pattern. The trained machine learning model can be used for determining a ranking of hot spots. In another method a model is trained based on measurement data to predict ranking of the hot spots.

公开(公告)号：US11544440B2

公开(公告)日：2023-01-03

申请号：US15734141

申请日：2019-05-23

Applicant: ASML NETHERLANDS B.V.

Inventor： Marinus Aart Van Den Brink ,  Yu Cao ,  Yi Zou

IPC: G06F30/398 ,  G06F30/392 ,  G06F119/18

Abstract: A method for calibrating a process model and training an inverse process model of a patterning process. The training method includes obtaining a first patterning device pattern from simulation of an inverse lithographic process that predicts a patterning device pattern based on a wafer target layout, receiving wafer data corresponding to a wafer exposed using the first patterning device pattern, and training an inverse process model configured to predict a second patterning device pattern using the wafer data related to the exposed wafer and the first patterning device pattern.

公开(公告)号：US11443083B2

公开(公告)日：2022-09-13

申请号：US16300380

申请日：2017-04-20

Applicant: ASML NETHERLANDS B.V.

Inventor： Jing Su ,  Yi Zou ,  Chenxi Lin ,  Stefan Hunsche ,  Marinus Jochemsen ,  Yen-Wen Lu ,  Lin Lee Cheong

IPC: G06T7/00 ,  G06F30/20 ,  G03F7/20 ,  G06K9/62 ,  G06F30/398 ,  G06N20/00

Abstract: Methods of identifying a hot spot from a design layout or of predicting whether a pattern in a design layout is defective, using a machine learning model. An example method disclosed herein includes obtaining sets of one or more characteristics of performance of hot spots, respectively, under a plurality of process conditions, respectively, in a device manufacturing process; determining, for each of the process conditions, for each of the hot spots, based on the one or more characteristics under that process condition, whether that hot spot is defective; obtaining a characteristic of each of the process conditions; obtaining a characteristic of each of the hot spots; and training a machine learning model using a training set including the characteristic of one of the process conditions, the characteristic of one of the hot spots, and whether that hot spot is defective under that process condition.

公开(公告)号：US10670973B2

公开(公告)日：2020-06-02

申请号：US15573832

申请日：2016-04-29

Applicant: ASML Netherlands B.V.

Inventor： Yi Zou ,  Jing Su ,  Robert John Socha ,  Christopher Alan Spence ,  Duan-Fu Stephen Hsu

IPC: G06F17/50 ,  G03F7/20 ,  G06T7/90 ,  G06T11/00 ,  G06F30/00

Abstract: A method includes obtaining a sub-layout having an area that is a performance limiting spot, adjusting colors of patterns in the area, and determining whether the area is still a performance limiting spot. Another method includes decomposing patterns in a design layout into multiple sub-layouts; determining for at least one area in one of the sub-layouts, the likelihood of that a figure of merit is beyond its allowed range; and if the likelihood is above a threshold, that one sub-layout has a performance limiting spot. Another method includes: obtaining a design layout having a first group of patterns and a second group of patterns, wherein colors of the first group of patterns are not allowed to change and colors of the second group of patterns are allowed to change; and co-optimizing at least the first group of patterns, the second group of patterns and an illumination of a lithographic apparatus.