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    Multi-Transistor Stack Architecture
    11.
    发明申请
    Multi-Transistor Stack Architecture 有权

    公开(公告)号：US20220199471A1

    公开(公告)日：2022-06-23

    申请号：US17125700

    申请日：2020-12-17

    Applicant: Arm Limited

    Inventor： Amit Chhabra ,  David Victor Pietromonaco

    IPC: H01L21/822 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238

    Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

    Systems, Devices, and Methods of Charge-Based Storage Elements
    16.
    发明公开
    Systems, Devices, and Methods of Charge-Based Storage Elements 审中-公开

    公开(公告)号：US20240081038A1

    公开(公告)日：2024-03-07

    申请号：US17902798

    申请日：2022-09-02

    Applicant: Arm Limited

    Inventor： Divya Madapusi Srinivas Prasad ,  David Victor Pietromonaco ,  Brian Tracy Cline ,  Mudit Bhargave

    IPC: H01L27/108

    CPC classification number: H01L27/108

    Abstract: According to one implementation of the present disclosure, a circuit structure is configured to store charge in a charge-based storage element, where the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit. According to one implementation of the present disclosure, a method includes: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit; forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region; placing a first liner material in the opening and on remaining portions of the substrate and the STI region; and depositing a first metal layer in the opening on the first liner material.

    Systems, Devices, and Methods of Cache Memory
    17.
    发明公开
    Systems, Devices, and Methods of Cache Memory 审中-公开

    公开(公告)号：US20240021232A1

    公开(公告)日：2024-01-18

    申请号：US17866448

    申请日：2022-07-15

    Applicant: Arm Limited

    Inventor： Divya Madapusi Srinivas Prasad ,  Krishnendra Nathella ,  David Victor Pietromonaco

    IPC: G11C11/406 ,  G11C11/409

    CPC classification number: G11C11/40607 ,  G11C11/409

    Abstract: According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

    Memory Architecture
    18.
    发明申请
    Memory Architecture 有权

    公开(公告)号：US20220223610A1

    公开(公告)日：2022-07-14

    申请号：US17149138

    申请日：2021-01-14

    Applicant: Arm Limited

    Inventor： Amit Chhabra ,  David Victor Pietromonaco

    IPC: H01L27/112 ,  G11C7/06 ,  G11C7/10 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    Abstract: Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack.

    Method and apparatus for operating an electric motor
    19.
    发明授权
    Method and apparatus for operating an electric motor 有权

    公开(公告)号：US10938331B2

    公开(公告)日：2021-03-02

    申请号：US16430236

    申请日：2019-06-03

    Applicant: Arm Limited

    Inventor： David Victor Pietromonaco

    IPC: H02P27/08 ,  H02P25/086 ,  H02P25/08 ,  H02K19/10 ,  H02P25/092

    Abstract: Apparatus and methods are provided for operating an electric motor, comprising selectively energising the coils of a stator having a plurality of stator teeth, each stator tooth having a said coil mounted thereon. The stator coils of a subset of the stator teeth are energised during a given time period to attract a corresponding rotor tooth into alignment with each of the stator teeth in the subset over the given time period. The stator coil of at least one stator tooth in the subset is energised during a portion of the given time period before the at least one stator tooth overlaps the corresponding rotor tooth.

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