公开(公告)号：US20220336470A1

公开(公告)日：2022-10-20

申请号：US17829939

申请日：2022-06-01

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Fred Fishburn

IPC: H01L27/108

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

公开(公告)号：US20220122883A1

公开(公告)日：2022-04-21

申请号：US17072135

申请日：2020-10-16

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  M. Arif Zeeshan ,  Shantanu Kallakuri ,  Kelvin Chan

IPC: H01L21/768

Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.

公开(公告)号：US20220068923A1

公开(公告)日：2022-03-03

申请号：US17011729

申请日：2020-09-03

Applicant: Applied Materials, Inc.

Inventor： M. Arif Zeeshan ,  Kelvin Chan ,  Shantanu Kallakuri ,  Sony Varghese

IPC: H01L27/105 ,  C23C16/04 ,  C23C16/02

Abstract: In one embodiment, a method of selectively forming a deposit may include
providing a substrate, the substrate having a plurality of surface features, extending at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may include directing a reactive beam to the plurality of surface features, the reactive beam defining a non-zero angle of incidence with respect to a perpendicular to the plane of the substrate, wherein a seed layer is deposited on a first portion of the surface features, and is not deposited on a second portion of the surface features. The method may further include exposing the substrate to a reactive deposition process after the directing the reactive ion beam, wherein a deposit layer selectively grows over the seed layer.

公开(公告)号：US11152373B1

公开(公告)日：2021-10-19

申请号：US16868851

申请日：2020-05-07

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese

IPC: H01L27/108 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

公开(公告)号：US20200185228A1

公开(公告)日：2020-06-11

申请号：US16793683

申请日：2020-02-18

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Sony Varghese ,  Anthony Renau ,  Morgan Evans ,  Joseph C. Olson

IPC: H01L21/3065 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.

公开(公告)号：US12131948B2

公开(公告)日：2024-10-29

申请号：US18224904

申请日：2023-07-21

Applicant: Applied Materials, Inc.

Inventor： M. Arif Zeeshan ,  Kelvin Chan ,  Shantanu Kallakuri ,  Sony Varghese ,  John Hautala

IPC: H01L21/768 ,  H01L21/48

CPC classification number: H01L21/76879 ,  H01L21/486

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.

公开(公告)号：US20240334683A1

公开(公告)日：2024-10-03

申请号：US18613525

申请日：2024-03-22

Applicant: Applied Materials, Inc.

Inventor： Tong Liu ,  Sony Varghese ,  Zhijun Chen ,  Balasubramanian Pranatharthiharan ,  Anand N. Iyer

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer (e.g., tungsten (W)) on a top surface of the insulating dielectric islands and on the bitline metal stack.

公开(公告)号：US11749564B2

公开(公告)日：2023-09-05

申请号：US17028259

申请日：2020-09-22

Applicant: Applied Materials, Inc.

Inventor： M. Arif Zeeshan ,  Kelvin Chan ,  Shantanu Kallakuri ,  Sony Varghese ,  John Hautala

IPC: H01L21/768 ,  H01L21/48

CPC classification number: H01L21/76879 ,  H01L21/486

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.

公开(公告)号：US20230101155A1

公开(公告)日：2023-03-30

申请号：US17868156

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Fred Fishburn ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Sony Varghese ,  Gill Yong Lee

IPC: H01L27/108

Abstract: A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

公开(公告)号：US10930735B2

公开(公告)日：2021-02-23

申请号：US16793683

申请日：2020-02-18

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Sony Varghese ,  Anthony Renau ,  Morgan Evans ,  Joseph C. Olson

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3065 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/423

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.