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    Fanout module integrating a photonic integrated circuit
    11.
    发明授权
    Fanout module integrating a photonic integrated circuit 有权

    公开(公告)号：US11709327B2

    公开(公告)日：2023-07-25

    申请号：US17361033

    申请日：2021-06-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

    IPC: G02B6/42 ,  G02B6/43

    CPC classification number: G02B6/4274 ,  G02B6/425 ,  G02B6/4255 ,  G02B6/43

    Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

    SEMICONDUCTOR DEVICE WITH AN EMBEDDED ACTIVE DEVICE
    12.
    发明公开
    SEMICONDUCTOR DEVICE WITH AN EMBEDDED ACTIVE DEVICE 审中-公开

    公开(公告)号：US20230207544A1

    公开(公告)日：2023-06-29

    申请号：US17560691

    申请日：2021-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  Rahul Agarwal ,  Raja Swaminathan ,  Brett P. Wilkerson

    IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

    CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225

    Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.

    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    13.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220392882A1

    公开(公告)日：2022-12-08

    申请号：US17891444

    申请日：2022-08-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

    INTEGRATED CIRCUIT MODULE WITH INTEGRATED DISCRETE DEVICES
    15.
    发明申请
    INTEGRATED CIRCUIT MODULE WITH INTEGRATED DISCRETE DEVICES 审中-公开

    公开(公告)号：US20200185367A1

    公开(公告)日：2020-06-11

    申请号：US16215969

    申请日：2018-12-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milind S. Bhagavat ,  Rahul Agarwal

    IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56

    Abstract: In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials.

    MOLDED DIE LAST CHIP COMBINATION
    16.
    发明申请
    MOLDED DIE LAST CHIP COMBINATION 审中-公开

    公开(公告)号：US20200168549A1

    公开(公告)日：2020-05-28

    申请号：US16778815

    申请日：2020-01-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milind S. Bhagavat ,  Rahul Agarwal

    IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

    High-speed die connections using a conductive insert
    18.
    发明授权
    High-speed die connections using a conductive insert 有权

    公开(公告)号：US12237286B2

    公开(公告)日：2025-02-25

    申请号：US18455960

    申请日：2023-08-25

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Rahul Agarwal

    IPC: H01L23/00 ,  H01L23/528

    Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

    Glass core package substrates
    19.
    发明授权
    Glass core package substrates 有权

    公开(公告)号：US12080632B2

    公开(公告)日：2024-09-03

    申请号：US17489182

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

    IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

    CPC classification number: H01L23/4951 ,  H01L23/145 ,  H10B12/50

    Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

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