公开(公告)号：US08486795B2

公开(公告)日：2013-07-16

申请号：US13444855

申请日：2012-04-12

Applicant: Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract translation: 制造晶体管的方法包括：提供包括N型阱和P型阱的衬底; 在N型阱上分别形成第一栅极和P型阱上的第二栅极; 在所述第一门上形成第三间隔物; 在第一栅极的两侧在衬底中形成外延层; 在所述第二闸门上形成第四间隔物; 在所述第四间隔物的两侧形成覆盖所述外延层的表面和所述基板的表面的硅覆盖层; 以及分别在第一栅极和第二栅极的两侧形成第一源极/漏极掺杂区域和第二源极/漏极掺杂区域。

公开(公告)号：US20120309158A1

公开(公告)日：2012-12-06

申请号：US13154396

申请日：2011-06-06

Applicant: Wen-Han Hung ,  Tsai-Fu Chen ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成虚拟栅极; 在所述伪栅极和所述衬底上形成接触蚀刻停止层; 执行平面化处理以部分地去除接触蚀刻停止层; 部分去除虚拟门; 并对接触蚀刻停止层进行热处理。

公开(公告)号：US20120086054A1

公开(公告)日：2012-04-12

申请号：US12902159

申请日：2010-10-12

Applicant: Tzyy-Ming Cheng ,  Meng-Chi Tsai ,  Tsai-Fu Chen ,  Ta-Kang Lo ,  Wen-Han Hung ,  Shih-Fang Tzou ,  Chun-Yuan Wu

Inventor： Tzyy-Ming Cheng ,  Meng-Chi Tsai ,  Tsai-Fu Chen ,  Ta-Kang Lo ,  Wen-Han Hung ,  Shih-Fang Tzou ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L23/485 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties.

Abstract translation: 公开了半导体结构。 半导体结构包括设置在基板上的栅极结构，在栅极结构的两侧分别设置在基板中的源极和漏极，设置在源极上并电连接到源极的源极接触插塞和设置在漏极接触插塞 在漏极上方并与漏极电连接。 源极接触插塞和漏极接触插塞具有相对不对称的元件特性。