公开(公告)号：US07450649B2

公开(公告)日：2008-11-11

申请号：US10481856

申请日：2003-05-15

Applicant: Peter Gregorius ,  Armin Hanneberg

Inventor： Peter Gregorius ,  Armin Hanneberg

IPC: H04B3/00

CPC classification number: H04L25/0266 ,  H04L25/085

Abstract: The invention relates to a transmitter for transmission of digital data via a transmission line (10), comprising a current-driving digital/analogue converter (1) which is arranged at the input of the transmitter; a current-operated form filter (2) for forming the current pulses which are supplied from the digital/analogue converter; a line driver (5) which carries out current/voltage conversion; and a circuit for offset compensation (6), which is arranged in a feedback path (11). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.

Abstract translation: 本发明涉及一种用于经由传输线（10）传输数字数据的发射机，包括布置在发射机输入端的电流驱动数/模转换器（1） 用于形成从数字/模拟转换器提供的电流脉冲的电流操作形式滤波器（2） 执行电流/电压转换的线路驱动器（5）; 以及布置在反馈路径（11）中的偏移补偿电路（6）。 为了提高在发射机的输出端发送的脉冲的质量，本发明提出了在目前的基础上进行发射机的内部信号处理。

公开(公告)号：US20080222443A1

公开(公告)日：2008-09-11

申请号：US11813952

申请日：2006-01-04

Applicant: Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

Inventor： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

IPC: G06F1/08

CPC classification number: H03M9/00

Abstract: The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).

Abstract translation: 本发明涉及一种与时钟信号（clk_hr_i）同步控制的与设备（1）输入的连续时钟信号（clk_hr_i）同步的控制信号（evload_o，odload_o，st_chgclk_o，clk_o，st_chgclk_o，clk_o，stkorfiford_i） ，其中所述控制器（SE）具有：寄存器装置，用于登记包括多个位位置的至少一个设置信号（st_load_i，st_fiford_i），用于根据一个或多个位位置对时钟信号（clk_hr_i）的边沿进行计数的计数装置 设置分别登记在寄存器装置中的信号，以及同步和输出装置，用于使由计数装置计数的值与时钟信号（clk_hr_i）和登记的设置信号同步，并输出至少一个控制信号，其中寄存器装置， 计数装置和同步和输出装置被配置和彼此连接，使得输出控制信号取决于相应的 有效登记的设定信号占据（占据）多个时间位置中的一个，具有与时钟信号的前沿或后沿同步的半个时钟周期的整数倍的相位差。 控制器可以特别用于控制同步并行 - 串行转换器，用于将包括k位位置的并行输入信号转换为与时钟信号（clk_hr_i）同步的串行输出信号序列，该时钟信号（clk_hr_i）被提供在发送电路中 接口电路的即将到来的存储器生成（例如DDR4）的非常快的DDR DRAM半导体存储器组件。

公开(公告)号：US07269093B2

公开(公告)日：2007-09-11

申请号：US11264060

申请日：2005-10-31

Applicant: Peter Gregorius ,  Martin Streibl

Inventor： Peter Gregorius ,  Martin Streibl

IPC: G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/222

Abstract: A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a local clock signal having a predetermined phase relationship with respect to the input clock signal, and generating the sampling clock signal based on the local clock signal.

Abstract translation: 一种方法在具有分布在存储器件中的多个通信块的存储器件的通信块中产生采样时钟信号。 该方法包括在通信块中接收输入时钟信号，仅响应于输入时钟信号产生相对于输入时钟信号具有预定相位关系的本地时钟信号，并且基于该时钟信号产生采样时钟信号 本地时钟信号。

公开(公告)号：US20070208980A1

公开(公告)日：2007-09-06

申请号：US11343946

申请日：2006-01-30

Applicant: Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

Inventor： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

IPC: G01R31/28

CPC classification number: G06F13/4059

Abstract: A method of transmitting data between different clock domains includes receiving data bits on the basis of a receiving clock, sequentially storing the data bits in a ring buffer, simultaneously transmitting a number of the stored data bits from the ring buffer on the basis of a first transmitting clock, and transmitting the stored data bits from the ring buffer on the basis of a second transmitting clock.

Abstract translation: 一种在不同时钟域之间发送数据的方法包括：基于接收时钟接收数据比特，顺序地将数据比特存储在环形缓冲器中，同时基于第一 发送时钟，并且基于第二发送时钟从所述环形缓冲器发送所存储的数据比特。

公开(公告)号：US07221615B2

公开(公告)日：2007-05-22

申请号：US11242150

申请日：2005-10-04

Applicant: Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

Inventor： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1006 ,  G11C11/4096

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract translation: 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。

公开(公告)号：US20070104292A1

公开(公告)日：2007-05-10

申请号：US11267930

申请日：2005-11-04

Applicant: Peter Gregorius

Inventor： Peter Gregorius

IPC: H03D3/24

CPC classification number: H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/146 ,  H03L2207/50

Abstract: Methods and apparatus for timing recovery phase locked loops. One embodiment provides a phase detectors for generating phase difference signals on the basis of a received feedback signal and an input clock signal and an input data signal, respectively. A digital control unit is adapted to generate a control signal depending on the first and second phase difference signals A digitally controlled oscillator generates an output clock signal depending on the control signal. A feedback unit feeds the output clock signal to an input of the first phase detector as the feedback signal. And a data acquisition unit receives the data signal and the output clock signal of the digitally controlled oscillator to provide a data output signal synchronized to the output clock signal.

Abstract translation: 用于定时恢复锁相环的方法和装置。 一个实施例提供了一种相位检测器，用于分别基于接收到的反馈信号和输入时钟信号和输入数据信号产生相位差信号。 数字控制单元适于根据第一和第二相位差信号产生控制信号。数字控制振荡器根据控制信号产生输出时钟信号。 反馈单元将输出时钟信号馈送到第一相位检测器的输入作为反馈信号。 并且数据采集单元接收数字信号和数字控制振荡器的输出时钟信号，以提供与输出时钟信号同步的数据输出信号。

公开(公告)号：US07173877B2

公开(公告)日：2007-02-06

申请号：US10955177

申请日：2004-09-30

Applicant: Hermann Ruckerbauer ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

Inventor： Hermann Ruckerbauer ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC: G11C8/00

CPC classification number: G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract translation: 本发明涉及一种具有两条时钟线的存储器件的存储器系统。 本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控​​制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线 向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回 到存储器控制器的读时钟输入。 存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

公开(公告)号：US20070028028A1

公开(公告)日：2007-02-01

申请号：US11193184

申请日：2005-07-29

Applicant: Paul Wallner ,  Peter Gregorius

Inventor： Paul Wallner ,  Peter Gregorius

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G11C5/04 ,  G11C7/10

Abstract: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved. Each memory chip includes a rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a CAwD signal stream is to be sent to the own memory core and processed or re-driven to the next memory chip and whether a read data stream is to be taken from its own memory core or from a read data input interface to be re-driven to the next memory chip.

Abstract translation: 在具有环路向前架构的半导体存储器系统中，按照以下顺序将命令，地址和写入数据流以及以存储器芯片发送到基于协议的帧的形式的单独读取数据流：存储器控制器到第一存储器芯片 到第二存储器芯片到第三存储器芯片和第四存储器芯片，并且读取数据流从第四存储器芯片传送到存储器控制器。 对于每个命令，通常访问四个存储器芯片中的一个用于数据处理，而四个存储器芯片中的三个只能实现CAwD流的简单重新驱动并读取数据流流。 通过将未嵌入帧中的等级选择信号从存储器控制器分别传送到每个存储器芯片，可以实现对这些任务的更多灵活性。 每个存储器芯片包括等级选择切换部分，其接收单独传送的等级选择信号并从其中解码用于选择是否将CAwD信号流发送到自己的存储器核心并被处理或重新驱动到下一个存储器的信号状态 以及从其自己的存储器核心还是从读取的数据输入接口取出读取数据流以被重新驱动到下一个存储器芯片。

公开(公告)号：US20070025131A1

公开(公告)日：2007-02-01

申请号：US11192335

申请日：2005-07-29

Applicant: Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

Inventor： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

IPC: G11C5/06

CPC classification number: G11C5/04 ,  G11C5/06 ,  H05K1/142

Abstract: The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.

Abstract translation: 本发明包括半导体存储器模块和使用其的半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

公开(公告)号：US20060285424A1

公开(公告)日：2006-12-21

申请号：US11152769

申请日：2005-06-15

Applicant: Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

Inventor： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

IPC: G11C8/00

CPC classification number: G06F13/4243 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107

Abstract: A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized read data stream to a serial read data input terminal of a corresponding second interface circuit section of a succeeding same memory chip or to a memory controller.

Abstract translation: 在包括存储器核心，第一接口电路部分和第二接口电路部分的半导体存储器芯片中实现高速接口电路。 第一接口电路部分可连接到写数据/命令和地址信号总线，包括写数据/命令和地址重新驱动器/发射机路径（其可以是透明的）并且不包括任何时钟信号同步电路， 以及包括串行到并行转换和同步装置的主写信号路径，以与接收到的写数据/命令和地址信号的参考时钟信号同步并将并行转换的写入信号传送到存储器核。 第二接口电路部分可连接到读数据总线，并且包括用于将接收的串行读取数据发送和重新驱动到后续半导体存储器芯片的透明读取数据重新驱动器/发送器路径和用于插入并行的主读取信号路径 将串行转换的读取数据从存储器核心转换成接收到的串行读取数据流，将并行到串行转换的读取数据与参考时钟信号同步，并将串行读取数据流提供给串行读取数据输入端 相应的相同存储器芯片的相应的第二接口电路部分或存储器控制器。