公开(公告)号：US20120218132A1

公开(公告)日：2012-08-30

申请号：US13466608

申请日：2012-05-08

Applicant: Nang-Ping TU ,  Fu-Lung HSUEH ,  Mingo LIU ,  I-Fey WANG

Inventor： Nang-Ping TU ,  Fu-Lung HSUEH ,  Mingo LIU ,  I-Fey WANG

IPC: H03M1/66

CPC classification number: H03M1/66 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03M1/662 ,  H03M1/765

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract translation: 集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。 集成电路包括多个采样和保持（S / H）电路。 每个S / H电路与DAC电路耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

公开(公告)号：US08188898B2

公开(公告)日：2012-05-29

申请号：US12762535

申请日：2010-04-19

Applicant: Nang-Ping Tu ,  Fu-Long Hsueh ,  Mingo Liu ,  I-Fey Wang

Inventor： Nang-Ping Tu ,  Fu-Long Hsueh ,  Mingo Liu ,  I-Fey Wang

IPC: H03M1/66

CPC classification number: H03M1/66 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03M1/662 ,  H03M1/765

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract translation: 集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。 集成电路包括多个采样和保持（S / H）电路。 每个S / H电路与DAC电路中的一个耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

公开(公告)号：US20110032129A1

公开(公告)日：2011-02-10

申请号：US12762535

申请日：2010-04-19

Applicant: Nang-Ping TU ,  Fu-Long HSUEH ,  Mingo LIU ,  I-Fey WANG

Inventor： Nang-Ping TU ,  Fu-Long HSUEH ,  Mingo LIU ,  I-Fey WANG

IPC: H03M1/00

CPC classification number: H03M1/66 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03M1/662 ,  H03M1/765

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract translation: 集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。 集成电路包括多个采样和保持（S / H）电路。 每个S / H电路与DAC电路中的一个耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

公开(公告)号：US20100273286A1

公开(公告)日：2010-10-28

申请号：US12429305

申请日：2009-04-24

Applicant: Kai-Chih Liang ,  Hua-Shu Wu ,  Li-Chun Peng ,  Tsung-Cheng Huang ,  Mingo Liu ,  Nick Y.M. Shen ,  Allen Timothy Chang

Inventor： Kai-Chih Liang ,  Hua-Shu Wu ,  Li-Chun Peng ,  Tsung-Cheng Huang ,  Mingo Liu ,  Nick Y.M. Shen ,  Allen Timothy Chang

IPC: H01L21/30

CPC classification number: B81C1/00246 ,  B81B2201/0257 ,  B81C2201/056 ,  B81C2203/0714 ,  B81C2203/0728

Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.

Abstract translation: 提供了一种方法的实施例，其包括提供具有前侧和后侧的基底。 在衬底上形成CMOS器件。 在该基板上也形成有MEMS器件。 形成MEMS器件包括在衬底的前侧形成MEMS机械结构。 然后释放MEMS机械结构。 在基板的前侧形成有保护层。 保护层设置在释放的MEMS机械结构上（例如，保护MEMS结构）。 在保护层设置在MEMS机械结构上的同时处理衬底的背面。

公开(公告)号：US20090283841A1

公开(公告)日：2009-11-19

申请号：US12329677

申请日：2008-12-08

Applicant: Ping-Chun Yeh ,  Der-Chyang Yeh ,  Ruey-Hsin Liu ,  Mingo Liu

Inventor： Ping-Chun Yeh ,  Der-Chyang Yeh ,  Ruey-Hsin Liu ,  Mingo Liu

IPC: H01L29/872 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0814 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/872

Abstract: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.

Abstract translation: 集成电路结构具有形成在n型阱区上的金属硅化物层，形成在n型阱区上并环绕金属硅化物层的p型保护环。 金属硅化物层的外部部分延伸成与保护环的内边缘重叠，并且在金属硅化物层的内部部分与阱区域的接合处形成肖特基势垒。 导电接触件与金属硅化物层的内部部分和外部部分接触。