公开(公告)号：US5220656A

公开(公告)日：1993-06-15

申请号：US457413

申请日：1989-12-26

申请人： Fujio Itomitsu ,  Masahito Matsuo

发明人： Fujio Itomitsu ,  Masahito Matsuo

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30192 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/342

摘要： A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained as a result of decoding the instruction to be executed. The process makes it possible to reduce the size of a micro ROM by processing one instruction having various formats by the same micro-instruction.

摘要翻译： 提供了一种用于生成用于指令执行装置的执行控制信息（操作指定参数）的装置和方法。 该装置通过选择和组合从指令码的位中选择的参数（位域）和作为对要执行的指令进行解码的结果而获得的参数进行操作。 该处理使得可以通过相同的微指令处理具有各种格式的一个指令来减小微ROM的大小。

公开(公告)号：US07487338B2

公开(公告)日：2009-02-03

申请号：US10443768

申请日：2003-05-23

申请人： Masahito Matsuo

发明人： Masahito Matsuo

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3001 ,  G06F9/30185 ,  G06F9/34 ,  G06F9/382 ,  G06F9/3853

摘要： A MOD_SAT instruction indicating that a 16 bit saturation is to be carried out with respect to the operation of one of instructions executed in parallel is placed in the left container and an ADD instruction is placed in the right container. When the instruction decode unit decodes these instructions, the instruction decode unit indicates that the instruction execution unit executes the ADD instruction accompanying a saturation process. Accordingly, the operation of a great number of instructions can be modified by combining instructions and, therefore, the basic instruction length can be made short and it becomes possible to increase the code efficiency.

摘要翻译： 指示相对于并行执行的一个指令的操作执行16位饱和的MOD_SAT指令被放置在左容器中，并且ADD指令被放置在右容器中。 当指令解码单元解码这些指令时，指令解码单元指示指令执行单元执行伴随饱和处理的ADD指令。 因此，可以通过组合指令来修改大量指令的操作，因此可以缩短基本指令长度，并且可以提高代码效率。

公开(公告)号：US06408385B1

公开(公告)日：2002-06-18

申请号：US09602830

申请日：2000-06-23

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F940

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

摘要翻译： 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

公开(公告)号：US6112289A

公开(公告)日：2000-08-29

申请号：US143530

申请日：1998-08-28

申请人： Masahito Matsuo

发明人： Masahito Matsuo

IPC分类号： G06F9/38

CPC分类号： G06F9/3822 ,  G06F9/3853

摘要： A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judging whether or not a combination of the first instruction and the second instruction can be executed in parallel and a bus for transferring two data in parallel between an operand access unit and an integer operation unit. The data processor uses a superscalar technique. Two instructions having an operand interference can be executed in parallel at high speed and two instructions accessing a memory can be executed in parallel without considerable hardware.

摘要翻译： 数据处理器包括：指令解码单元，具有两个解码器，对由包括第一指令和第一指令之后的第二指令的多个指令组成的指令组的相应指令进行解码，以及判断单元，判断第一 指令和第二指令可并行执行，总线用于在操作数存取单元和整数运算单元之间并行传送两个数据。 数据处理器使用超标量技术。 可以高速并行地执行具有操作数干扰的两个指令，并且可以并行地执行访问存储器的两个指令，而没有相当大的硬件。

公开(公告)号：US5848268A

公开(公告)日：1998-12-08

申请号：US535870

申请日：1995-09-29

申请人： Masahito Matsuo

发明人： Masahito Matsuo

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

公开(公告)号：US5485587A

公开(公告)日：1996-01-16

申请号：US10085

申请日：1993-01-27

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

公开(公告)号：US5386580A

公开(公告)日：1995-01-31

申请号：US819545

申请日：1992-01-10

申请人： Toyohiko Yoshida ,  Masahito Matsuo

发明人： Toyohiko Yoshida ,  Masahito Matsuo

IPC分类号： G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/34 ,  G06F9/345 ,  G06F9/35 ,  G06F9/38

CPC分类号： G06F9/345 ,  G06F9/34

摘要： A data processor which comprises: an instruction decoding unit for decoding the instruction; an operand address calculating unit having an adder and an output latch holding the added result and calculating addresses of plural memory operands, in accordance with address calculation control code outputted from the instruction decoding unit; and an instruction executing unit for executing the instruction, in accordance with the operand address outputted from the operand address calculating unit and an operation control code outputted from the instruction decoding unit; and is capable of executing the plural data operating instruction for processing plural data at high efficiency, by performing address calculation of the plural operands by the operand address calculating unit before executing the instruction by the instruction executing unit.

摘要翻译： 一种数据处理器，包括：指令解码单元，用于解码指令; 操作数地址计算单元，具有根据从指令解码单元输出的地址计算控制码，具有加法器和保存相加结果的输出锁存器以及计算多个存储器操作数的地址; 以及指令执行单元，用于根据从操作数地址计算单元输出的操作数地址和从指令解码单元输出的操作控制代码执行指令; 并且能够通过由指令执行单元执行指令之前通过操作数地址计算单元执行多个操作数的地址计算，来执行用于高效率处理多个数据的多个数据操作指令。

公开(公告)号：US5349681A

公开(公告)日：1994-09-20

申请号：US821802

申请日：1992-01-16

申请人： Toyohiko Yoshida ,  Masahito Matsuo

发明人： Toyohiko Yoshida ,  Masahito Matsuo

IPC分类号： G06F9/30 ,  G06F7/74 ,  G06F9/305 ,  G06F9/308 ,  G06F9/34 ,  G06F12/00 ,  G06F9/312

CPC分类号： G06F7/74 ,  G06F9/30018

摘要： A bit searching circuit includes an offset value designating circuit, a bit position detecting circuit, a count circuit, and a search-end detecting circuit. The offset value designating circuit outputs an offset value indicating a search-start position. The bit position detecting circuit searches for the first bit position which has a first binary value, in a search field between the bit position designated by the offset value and a last bit position in a bit string. The count circuit counts the number of bits in the search field having the first binary value. The search-end detecting circuit detects the end of search processing by subtracting the bit counts detected by the bit position detecting circuit from the count value counted by the count circuit until the result is zero. A data processor using such a bit searching circuit includes a control unit and an instruction execution unit. The control unit includes a decoding circuit, decoding an operation code field of an instruction for operating on plural data where the instruction includes a register list indicating the register numbers storing data to be operated on. The bit searching circuit searches the register list represented by a bit string field consisting of binary values, and controls execution of the instruction. The instruction executing unit executes the instruction.

摘要翻译： 位搜索电路包括偏移值指定电路，位位置检测电路，计数电路和搜索结束检测电路。 偏移值指定电路输出表示搜索开始位置的偏移值。 比特位置检测电路在由偏移值指定的比特位置和比特串中的最后比特位置之间的搜索字段中搜索具有第一二进制值的第一比特位置。 计数电路对具有第一二进制值的搜索字段中的位数进行计数。 搜索结束检测电路通过从由计数电路计数的计数值减去由比特位置检测电路检测的比特计数直到结果为零来检测搜索结束结束。 使用这种位搜索电路的数据处理器包括控制单元和指令执行单元。 控制单元包括解码电路，用于解码用于操作多个数据的指令的操作码字段，其中该指令包括指示存储要操作的数据的寄存器号的寄存器列表。 位搜索电路搜索由由二进制值组成的位串字段表示的寄存器列表，并控制指令的执行。 指令执行单元执行指令。

公开(公告)号：US5313644A

公开(公告)日：1994-05-17

申请号：US619852

申请日：1990-11-28

申请人： Masahito Matsuo ,  Toru Shimizu

发明人： Masahito Matsuo ,  Toru Shimizu

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/06

CPC分类号： G06F9/30094 ,  G06F9/30101 ,  G06F9/3885

摘要： A data processing system which is provided with a plurality of operation units and a function which executes a plurality of instructions in parallel by each of these plurality of operation units, respectively, wherein operation results executed by these plurality of operation units are reflected on flags which are included in a processor status word (PSW), thereby, those plurality of instructions are executed in parallel in the respective different operation units, and at that time, results of operation processing of the respective instructions are reflected on the flags included in the PSW, then, the flags can be updated by simple control, and the operation results executed by those plurality of operation units are reflected on the flags included in the PSW according to the order of execution of the instructions, thereby, those plurality of instructions are executed in parallel by the respective different operation units, and at that time, the results of operation processing of the respective instructions are reflected on the flags included in the PSW according to the order of execution of the instructions, whereby enabling to realize the high speed operation without providing such complicated processing as temporarily saving information for reflecting the results of operation processing on the flags until processing of the preceding instructions is finished.

摘要翻译： 一种数据处理系统，其具有多个操作单元和分别执行多个操作单元中的每一个并行执行多个指令的功能，其中由这些多个操作单元执行的操作结果被反映在 被包括在处理器状态字（PSW）中，从而在各个不同的操作单元中并行地执行那些多个指令，并且此时各个指令的操作处理结果被反映在包括在PSW中的标志 ，则可以通过简单的控制来更新标志，并且由多个操作单元执行的操作结果根据指令的执行顺序反映在包含在PSW中的标志上，从而执行这些多个指令 并行地由各自的不同的操作单元组成，并且当时的操作处理结果 观察指令根据指令执行顺序反映在PSW中包含的标志上，从而能够实现高速操作，而不需要提供诸如暂时保存用于反映标志上的操作处理结果的信息的复杂处理，直到处理 的上述说明完成。

公开(公告)号：US4974154A

公开(公告)日：1990-11-27

申请号：US106604

申请日：1987-10-06

申请人： Masahito Matsuo

发明人： Masahito Matsuo

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3844

摘要： A computer comprises an instruction execution unit for running a first instruction loaded in an area classified by a first area recognition symbol of a storage for loading a plurality of instructions in a plurality of areas ordered by the area recognition symbols. An instruction analyzer (instruction decoding unit) is connected to said instruction execution unit for analyzing a second instruction loaded in an area classified by a second area recognition symbol. An instruction prefetch queue is connected between the instruction decoding unit and the main memory storage. A target prediction unit (branch target buffer) for predicting whether or not the second instruction is a branch instruction for running a fourth instruction loaded in an area classified by a fourth area recognition symbol is connected to the instruction prefetch queue, and an instruction prefetch queue retreat unit, wherein a part or all of the third instructions fetched in the instruction prefetch unit is stored temporarily when the target prediction unit predicts that the fourth instruction will be executed after instruction of the second instruction, is connected to the instruction prefetch queue and the instruction analyzer.

摘要翻译： 计算机包括指令执行单元，用于运行加载在由区域识别符号排序的多个区域中的用于加载多个指令的存储器的第一区域识别符号分类的区域中的第一指令。 指令分析器（指令解码单元）连接到所述指令执行单元，用于分析加载在由第二区域识别符号分类的区域中的第二指令。 指令预取队列连接在指令解码单元和主存储器之间。 用于预测第二指令是否是用于运行加载在由第四区域识别符号分类的区域中的第四指令的分支指令的目标预测单元（分支目标缓冲器）连接到指令预取队列，以及指令预取队列 撤销单元，其中当所述目标预测单元预测在所述第二指令的指令之后执行所述第四指令时，暂时存储在所述指令预取单元中取出的所述第三指令的一部分或全部，连接到所述指令预取队列，并且 指令分析仪