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    Transimpedance amplifier
    12.
    发明授权
    Transimpedance amplifier 有权
    互阻放大器

    公开(公告)号：US07688134B2

    公开(公告)日：2010-03-30

    申请号：US11990871

    申请日：2006-07-24

    Applicant: Masahiro Tanomura ,  Kouji Matsunaga

    Inventor： Masahiro Tanomura ,  Kouji Matsunaga

    IPC: H03F1/34

    CPC classification number: H03F1/42 ,  H03F1/08 ,  H03F1/34 ,  H03F2200/36

    Abstract: The present invention solves characteristic deterioration caused by peaking and a ground inductance, and provides a transimpedance amplifier capable of achieving a higher gain and a wider band. For this purpose, the transimpedance amplifier is configured to include a feedback circuit having two or more extreme frequencies and having a filter characteristic which is flat with respect to frequencies in a frequency region not more than a smallest extreme frequency among the extreme frequencies, which is flat with respect to frequencies in a frequency region not less than a largest extreme frequency among the extreme frequencies, and which has at least one negative inclination portion with respect to frequencies in a frequency region between the smallest and largest extreme frequencies.

    Abstract translation: 本发明解决了由峰值和接地电感引起的特性劣化，并且提供了能够实现更高增益和更宽带的跨阻放大器。 为此，跨阻放大器被配置为包括具有两个或多个极端频率的反馈电路，并且具有相对于极端频率中不超过最小极端频率的频率区域中的频率为平坦的滤波器特性，其为 相对于极端频率以上的最大极端频率以上的频率区域中的频率平坦，并且相对于最小和最大极端频率之间的频率区域中的频率具有至少一个负倾斜部分。

    Semiconductor Device
    13.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20080230807A1

    公开(公告)日：2008-09-25

    申请号：US11547402

    申请日：2005-03-30

    Applicant: Naotaka Kuroda ,  Masahiro Tanomura ,  Naoto Kurosawa

    Inventor： Naotaka Kuroda ,  Masahiro Tanomura ,  Naoto Kurosawa

    IPC: H01L29/73 ,  H01L23/34

    CPC classification number: H01L29/7371 ,  H01L23/367 ,  H01L27/0605 ,  H01L27/0664 ,  H01L29/66318 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.

    Abstract translation: 提供具有足够高的散热性能同时抑制芯片面积的增加的半导体器件。 在半导体器件1中，多个HBT 20和多个二极管30一维地交替地布置在半导体衬底10上。 二极管30的阳极电极36通过公共发射极配线42连接到HBT 20的发射极27。 二极管30作为散热元件散发到半导体衬底10上，从发射极27传播通过公共发射极配线42的热，并且还用作并联连接在HBT 20的发射极和集电极之间的保护二极管。

    Heterojunction bipolar transistor with reduced offset voltage
    14.
    发明授权
    Heterojunction bipolar transistor with reduced offset voltage 失效
    具有降低偏移电压的异质结双极晶体管

    公开(公告)号：US06492664B2

    公开(公告)日：2002-12-10

    申请号：US09874078

    申请日：2001-06-05

    Applicant: Masahiro Tanomura

    Inventor： Masahiro Tanomura

    IPC: H01L31072

    CPC classification number: H01L29/66318 ,  H01L29/0821 ,  H01L29/7371

    Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer, and an emitter layer stacked sequentially. The base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.

    Abstract translation: 异质结双极晶体管包括依次堆叠的集电极层，基极层和发射极层。 基底层包括在发射极层正下方的向内基底区域中与集电极层接合的第一基底层和在与向内基部区域相邻的外部基底区域中与收集层连接的第二基底层。 第二基层由具有比集电极层更宽的能带隙的半导体形成。

    NITRIDE SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    16.
    发明申请
    NITRIDE SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开
    氮化物半导体器件和电子器件

    公开(公告)号：US20120241759A1

    公开(公告)日：2012-09-27

    申请号：US13501891

    申请日：2010-10-15

    Applicant: Koji Matsunaga ,  Masahiro Tanomura

    Inventor： Koji Matsunaga ,  Masahiro Tanomura

    IPC: H01L29/20

    CPC classification number: H01L29/7787 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/872

    Abstract: A nitride semiconductor device having a high withstand voltage and being capable of reducing a leakage current, is provided. The nitride semiconductor device 30 of the present invention includes: a nitride semiconductor stack; an anode 36; and cathodes 37 and 38. The nitride semiconductor stack includes: a channel layer 33 and a wide bandgap layer 35, stacked in this order. The anode 36 forms a Schottky junction with the wide bandgap layer 35. The cathodes 37 and 38 are joined to the channel layer 33. The channel layer 33 is an n+-type nitride semiconductor layer. The bandgap of the wide bandgap layer 35 is wider than that of the channel layer 33.

    Abstract translation: 提供具有高耐受电压并且能够减小漏电流的氮化物半导体器件。 本发明的氮化物半导体器件30包括：氮化物半导体叠层; 阳极36; 和阴极37和38.氮化物半导体堆叠包括：按顺序堆叠的沟道层33和宽带隙层35。 阳极36与宽带隙层35形成肖特基结。阴极37和38连接到沟道层33.沟道层33是n +型氮化物半导体层。 宽带隙层35的带隙比沟道层33的带隙宽。

    SIMULATION DEVICE, SIMULATION METHOD, AND RECORDING MEDIUM STORING PROGRAM
    17.
    发明申请
    SIMULATION DEVICE, SIMULATION METHOD, AND RECORDING MEDIUM STORING PROGRAM 失效
    模拟装置，模拟方法和记录存储程序

    公开(公告)号：US20110224964A1

    公开(公告)日：2011-09-15

    申请号：US13129341

    申请日：2009-09-17

    Applicant: Masahiro Tanomura

    Inventor： Masahiro Tanomura

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: Provided are a device model, a recording medium storing a program, a simulation circuit, device, and method that calculate a local temperature increase in an element. The device model according to the present invention is used for a semiconductor circuit simulation and has at least two model parameters. The model parameters include an electrical model describing temperature characteristics and a thermal model describing thermal characteristics and corresponding to the electrical model.

    Abstract translation: 提供了一种计算元件中的局部温度升高的装置型号，存储程序的记录介质，模拟电路，装置和方法。 根据本发明的器件模型用于半导体电路仿真，并且具有至少两个模型参数。 模型参数包括描述温度特性的电气模型和描述热特性并对应于电气模型的热模型。

    Semiconductor device and method of manufacturing the same
    19.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06403436B1

    公开(公告)日：2002-06-11

    申请号：US09619337

    申请日：2000-07-19

    Applicant: Masahiro Tanomura

    Inventor： Masahiro Tanomura

    IPC: H01L21331

    CPC classification number: H01L29/66318 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0658 ,  H01L29/7371 ,  H01L29/8605

    Abstract: Subcollector layers or emitter layers constituting a bipolar transistor having different thicknesses form a two-layered structure. A resistor layer is formed at the same as one of the subcollector layers or one of the emitter layers, from the same material as that of the subcollector layer or emitter layer. A resistor is formed by the resistor layer made of the same material as that of the subcollector layer or emitter layer. A resistor with a desired resistance can be integrally built into a semiconductor device without adversely affecting the characteristics of a bipolar transistor.

    Abstract translation: 构成具有不同厚度的双极晶体管的子集电极层或发射极层形成两层结构。 与子集电极层或发射极层相同的材料与子集电极层之一或发射极层之一形成电阻层。 电阻器由与子集电极层或发射极层相同的材料制成的电阻层形成。 具有期望电阻的电阻器可以一体地内置在半导体器件中，而不会不利地影响双极晶体管的特性。

    Simulation device, simulation method, and recording medium storing program
    20.
    发明授权
    Simulation device, simulation method, and recording medium storing program 失效
    仿真设备，仿真方法和记录介质存储程序

    公开(公告)号：US08630835B2

    公开(公告)日：2014-01-14

    申请号：US13129341

    申请日：2009-09-17

    Applicant: Masahiro Tanomura

    Inventor： Masahiro Tanomura

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: Provided are a device model, a recording medium storing a program, a simulation circuit, device, and method that calculate a local temperature increase in an element. The device model according to the present invention is used for a semiconductor circuit simulation and has at least two model parameters. The model parameters include an electrical model describing temperature characteristics and a thermal model describing thermal characteristics and corresponding to the electrical model.

    Abstract translation: 提供了一种计算元件中的局部温度升高的装置型号，存储程序的记录介质，模拟电路，装置和方法。 根据本发明的器件模型用于半导体电路仿真，并且具有至少两个模型参数。 模型参数包括描述温度特性的电气模型和描述热特性并对应于电气模型的热模型。

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