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    Visibility packets with inflated latency
    11.
    发明授权
    Visibility packets with inflated latency 有权

    公开(公告)号：US11044204B1

    公开(公告)日：2021-06-22

    申请号：US16527278

    申请日：2019-07-31

    Applicant: Innovium, Inc.

    Inventor： William Brad Matthews ,  Puneet Agarwal

    IPC: H04L12/825 ,  H04L12/26

    Abstract: Nodes within a network are configured to adapt to changing path states, due to congestion, node failures, and/or other factors. A node may selectively convey path information and/or other state information to another node by annotating the information into packets it receives from the other node. A node may selectively reflect these annotated packets back to the other node, or other nodes that subsequently receive these annotated packets may reflect them. A weighted cost multipathing selection technique is improved by dynamically adjusting weights of paths in response to feedback indicating the current state of the network topology, such as collected through these reflected packets. In an embodiment, certain packets that would have been dropped may instead be transformed into “special visibility” packets that may be stored and/or sent for analysis. In an embodiment, insight into the performance of a network device is enhanced through the use of programmable visibility engines.

    Shared buffer memory architecture
    12.
    发明授权
    Shared buffer memory architecture 有权

    公开(公告)号：US10884829B1

    公开(公告)日：2021-01-05

    申请号：US16867490

    申请日：2020-05-05

    Applicant: Innovium, Inc.

    Inventor： Mohammad Kamel Issa

    IPC: G06F3/00 ,  G06F9/54 ,  G06F9/52 ,  G11C7/22 ,  G06F9/30 ,  G11C7/10 ,  G06F9/48

    Abstract: An improved buffer for networking devices and other computing devices comprises multiple memory instances, each having a distinct set of entries. Transport data units (“TDUs”) are divided into storage data units (“SDUs”), and each SDU is stored within a separate entry of a separate memory instance in a logical bank. A grid of the memory instances is organized into overlapping horizontal logical banks and vertical logical banks. A memory instance may be shared between horizontal and vertical logical banks. When overlapping logical banks are accessed concurrently, the memory instance that they share may be inaccessible to one of the logical banks. Accordingly, when writing a TDU, a parity SDU may be generated for the TDU and also stored within its logical bank. The TDU's content within the shared memory instance may then be reconstructed from the parity SDU without having to read the shared memory instance.

    Intelligent packet queues with delay-based actions
    13.
    发明授权
    Intelligent packet queues with delay-based actions 有权

    公开(公告)号：US10673770B1

    公开(公告)日：2020-06-02

    申请号：US16288165

    申请日：2019-02-28

    Applicant: Innovium, Inc.

    Inventor： William Brad Matthews ,  Puneet Agarwal ,  Ajit Kumar Jain

    IPC: H04L12/863 ,  H04L12/801 ,  H04L12/26

    Abstract: A network device organizes packets into various queues, in which the packets await processing. Queue management logic tracks how long certain packet(s), such as a designated marker packet, remain in a queue. Based thereon, the logic produces a measure of delay for the queue, referred to herein as the “queue delay.” Based on a comparison of the current queue delay to one or more thresholds, various associated delay-based actions may be performed, such as tagging and/or dropping packets departing from the queue, or preventing addition enqueues to the queue. In an embodiment, a queue may be expired based on the queue delay, and all packets dropped. In other embodiments, when a packet is dropped prior to enqueue into an assigned queue, copies of some or all of the packets already within the queue at the time the packet was dropped may be forwarded to a visibility component for analysis.

    Traffic analyzer for autonomously configuring a network device
    14.
    发明授权
    Traffic analyzer for autonomously configuring a network device 有权

    公开(公告)号：US10652154B1

    公开(公告)日：2020-05-12

    申请号：US16186369

    申请日：2018-11-09

    Applicant: Innovium, Inc.

    Inventor： William Brad Matthews ,  Bruce Hui Kwan

    IPC: H04L12/803 ,  H04L12/947 ,  H04L12/24 ,  G06N3/08 ,  G06N5/02 ,  G06N20/00 ,  H04W52/02

    Abstract: Approaches, techniques, and mechanisms facilitate actionable reporting of network state information and real-time, autonomous network engineering directly in-network at a switch or other network device. A data collector within the network device collects state information and/or data unit information from various device components, such as traffic managers and packet processors. The data collector, which may optionally generate additional state information by performing various calculations on the information it receives, is configured to then provide at least some of the state information to an analyzer device connected to an analyzer interface. The analyzer device, which may be a separate device, performs various analyses on the state information, depending on how it is configured. The analyzer device outputs reports that identify statuses, errors, misconfigurations, and/or suggested actions to take to improve operation of the network device. In an embodiment, some or all actions that may be suggested therein are executed automatically.

    Scalable ingress arbitration for merging control and payload
    15.
    发明授权
    Scalable ingress arbitration for merging control and payload 有权

    公开(公告)号：US10554572B1

    公开(公告)日：2020-02-04

    申请号：US15433825

    申请日：2017-02-15

    Applicant: Innovium, Inc.

    Inventor： William Brad Matthews ,  Paul Roy Kim ,  Puneet Agarwal

    IPC: H04L12/865 ,  H04L12/863 ,  H04L29/06

    Abstract: Approaches, techniques, and mechanisms are disclosed for improving the efficiency with which data units are handled within a device, such as a networking device. Received data units, or portions thereof, are temporarily stored within one or more memories of a merging component, while the merging component waits to receive control information for the data units. Once received, the merging component merges the control information with the associated data units. The merging component dispatches the merged data units, or portions thereof, to an interconnect component, which forwards the merged data units to destinations indicated by the control information. The device is configured to intelligently schedule the dispatching of merged data units to the interconnect component. To this end, the device includes a scheduler configured to select which merged data units to dispatch at which times based on a variety of factors described herein.

    Enhanced prefix matching
    16.
    发明授权
    Enhanced prefix matching 有权

    公开(公告)号：US10230639B1

    公开(公告)日：2019-03-12

    申请号：US15671151

    申请日：2017-08-08

    Applicant: Innovium, Inc.

    Inventor： Vasant Shankargouda Patil ,  Puneet Agarwal ,  Gururaj Ananthateerta ,  Rupa Budhia

    IPC: H04L12/745 ,  H04L12/753 ,  H04L12/743 ,  G06F16/22 ,  G06F16/2453

    Abstract: Approaches, techniques, and mechanisms are disclosed for maintaining efficient representations of prefix tables for utilization during the operation of a network device. In an embodiment, the performance of a network device is greatly enhanced using a working representation of a prefix table that includes a prefix index and a plurality of associated prefix arrays. In an embodiment, this working representation is bifurcated across a higher-performing memory for the prefix index and a lower-performing memory for the prefix arrays. In an embodiment, management of this working representation is greatly simplified using a sharded prefix tree that is divided into subtrees based on constraints of the memory in which this working representation is stored. In yet another embodiment, a sharded prefix tree may itself be utilized to more efficiently find a longest prefix match for an input key.

    SYSTEM AND METHOD FOR ENABLING HIGH READ RATES TO DATA ELEMENT LISTS
    17.
    发明申请
    SYSTEM AND METHOD FOR ENABLING HIGH READ RATES TO DATA ELEMENT LISTS 审中-公开

    公开(公告)号：US20180081577A1

    公开(公告)日：2018-03-22

    申请号：US15815854

    申请日：2017-11-17

    Applicant: Innovium, Inc.

    Inventor： William Brad Matthews ,  Bruce H. Kwan ,  Mohammad K. Issa ,  Neil Barrett ,  Avinash Gyanendra Mani

    IPC: G06F3/06 ,  G06F12/06

    Abstract: A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.

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