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    Level shift circuit, integrated circuit, electronic device
    12.
    发明授权
    Level shift circuit, integrated circuit, electronic device 有权

    公开(公告)号：US12199614B2

    公开(公告)日：2025-01-14

    申请号：US18081922

    申请日：2022-12-15

    Applicant: Beijing ESWIN Computing Technology Co., Ltd. ,  Hefei ESWIN Computing Technology Co., Ltd.

    Inventor： Xiaoheng Zhang ,  Jiajhang Wu ,  Haohao Zhang

    IPC: H03K19/0175 ,  H03K3/356 ,  H03K19/0185 ,  H03M1/66

    Abstract: The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

    Level shift circuit, chip and display device
    17.
    发明授权
    Level shift circuit, chip and display device 有权

    公开(公告)号：US12206408B2

    公开(公告)日：2025-01-21

    申请号：US18147500

    申请日：2022-12-28

    Applicant: Beijing ESWIN Computing Technology Co., Ltd. ,  Hefei ESWIN Computing Technology Co., Ltd.

    Inventor： Jiajhang Wu ,  Sangmin Park ,  Minsung Kim

    IPC: H03K19/003 ,  G09G3/36 ,  H03K19/0185

    Abstract: Embodiments of the disclosure provide a level shift circuit, a chip and a display device. By setting first and second voltage clamping modules, and by adjusting first clamping voltage by controlling bias voltage input to the first voltage clamping module and adjusting second clamping voltage by controlling bias voltage and second bias voltage input to the second voltage clamping module, respective operating and output voltages of the first and the second voltage clamping modules and the shift module are within small range. Therefore, even the level shift circuit is designed by using devices with breakdown voltage lower than the difference between the first and second power supply voltages, the devices in the level shift circuit may be avoid being breakdown. Accordingly, some process platforms that cannot produce high-breakdown voltage devices may produce chips including the level shift circuit in the embodiment, and the restrictions on the process platform are reduced.

    DRIVE CONTROL METHOD APPLICABLE TO TIMING CONTROLLER, AND DRIVE CIRCUIT
    18.
    发明申请
    DRIVE CONTROL METHOD APPLICABLE TO TIMING CONTROLLER, AND DRIVE CIRCUIT 有权

    公开(公告)号：US20240412674A1

    公开(公告)日：2024-12-12

    申请号：US18808420

    申请日：2024-08-19

    Applicant: Beijing ESWIN Computing Technology Co., Ltd. ,  Hefei ESWIN Computing Technology Co., Ltd.

    Inventor： Jangjin NAM ,  Dongmyung LEE ,  Donghoon BAEK ,  Daejoon LEE

    IPC: G09G3/20 ,  G09G3/36

    Abstract: A drive control method applicable to a timing controller and a drive circuit are provided. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

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