公开(公告)号：US20060228876A1

公开(公告)日：2006-10-12

申请号：US11101639

申请日：2005-04-08

Applicant: Olaf Storbeck ,  Jens Hahn ,  Sven Schmidbauer ,  Juergen Faul ,  Frank Jakubowski ,  Thomas Schuster

Inventor： Olaf Storbeck ,  Jens Hahn ,  Sven Schmidbauer ,  Juergen Faul ,  Frank Jakubowski ,  Thomas Schuster

IPC: H01L29/00

CPC classification number: H01L21/265 ,  H01L21/28044 ,  H01L21/324 ,  H01L29/4925

Abstract: The invention relates to a method of manufacturing a semiconductor device, in which a substrate is provided, a dielectric layer is formed on top of the substrate, an amorphous semiconductor layer id deposited on top of the dielectric layer, the amorphous semiconductor layer is doped, and a high temperature step to the amorphous layer is applied to form a crystallized layer out of the amorphous semiconductor.

Abstract translation: 本发明涉及一种制造半导体器件的方法，其中提供了一种衬底，在衬底的顶部形成介电层，淀积在电介质层顶部的非晶半导体层，掺杂非晶半导体层， 并且施加到非晶层的高温步骤以从非晶半导体形成结晶层。

公开(公告)号：US06967133B2

公开(公告)日：2005-11-22

申请号：US10696159

申请日：2003-10-29

Applicant: Jürgen Amon ,  Jürgen Faul ,  Ulrike Gruening ,  Frank Jakubowski ,  Thomas Schuster ,  Rudolf Strasser

Inventor： Jürgen Amon ,  Jürgen Faul ,  Ulrike Gruening ,  Frank Jakubowski ,  Thomas Schuster ,  Rudolf Strasser

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC classification number: H01L27/10888 ,  H01L21/26586 ,  H01L21/28512 ,  H01L29/66659

Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).

Abstract translation: 本发明提供了一种在半导体衬底（10）上制造具有多个栅极堆叠（GS 1，GS 2，GS 3，GS 4）的半导体结构的方法，具有以下步骤：施加栅极堆叠（GS 1，GS 2，GS 3，GS 4）连接到半导体衬底（10）上方的栅极电介质（11）; 在栅堆叠（GS 1，GS 2，GS 3，GS 4）的侧壁上形成侧壁氧化物（17）; 半导体结构上的掩模（12）的应用和图案化; 以及在未被掩模（12）覆盖的区域中相对于栅极堆叠（GS1，GS2）的侧壁氧化物（17）以自对准的方式注入接触掺杂（13）。

公开(公告)号：US09023715B2

公开(公告)日：2015-05-05

申请号：US13454520

申请日：2012-04-24

Applicant: Juergen Faul ,  Frank Jakubowski

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2255 ,  H01L29/66803

Abstract: Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.

Abstract translation: 公开了形成体FinFET半导体器件以减少穿透漏电流的方法。 一个实例包括在半导体衬底中形成多个沟槽以限定多个间隔开的散热片，在沟槽中形成绝缘材料的掺杂层，其中每个鳍的暴露部分在掺杂的上表面上方延伸 绝缘材料层，而每个鳍片的覆盖部分位于绝缘材料的掺杂层的上表面的下方，并且进行加工操作以至少加热绝缘材料的掺杂层，以使掺杂物质掺杂 层从绝缘材料的掺杂层迁移到鳍的被覆盖部分中，从而在翅片的被覆盖部分中限定位于翅片的暴露部分下方的掺杂区域。

公开(公告)号：US08716102B2

公开(公告)日：2014-05-06

申请号：US13584981

申请日：2012-08-14

Applicant: Frank Jakubowski ,  Joerg Radecker ,  Joanna Wasyluk

Inventor： Frank Jakubowski ,  Joerg Radecker ,  Joanna Wasyluk

IPC: H01L27/092

CPC classification number: H01L21/76224 ,  H01L21/02065 ,  H01L21/31053 ,  H01L21/31116

Abstract: A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.

Abstract translation: 一种方法包括形成图案化掩模，其由位于衬底上方的保护层上方的抛光停止层构成，通过衬底上的图案化掩模层执行至少一个蚀刻工艺，以在衬底中形成沟槽，并形成硅层 在图案化掩模层之上的二氧化硅，使得二氧化硅层过度填充沟槽。 该方法还包括去除位于沟槽外部的二氧化硅层的部分以限定隔离结构，执行干燥的选择性化学氧化物蚀刻工艺，其相对于抛光停止层的材料选择性地去除二氧化硅以减少整体 隔离结构的高度，并且进行选择性湿蚀刻工艺以相对于隔离区选择性地去除抛光停止层。

公开(公告)号：US08603895B1

公开(公告)日：2013-12-10

申请号：US13610263

申请日：2012-09-11

Applicant: Frank Jakubowski ,  Joerg Radecker ,  Ralf Willecke

Inventor： Frank Jakubowski ,  Joerg Radecker ,  Ralf Willecke

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: In one example, the method includes forming a patterned etch mask above a semiconducting substrate, performing an etching process through the patterned etch mask to thereby form a trench in the substrate, performing a first deposition process to form a first layer of insulating material above the patterned etch mask and in the trench, and performing an etching process on the first layer of insulating material such that the post-etch thickness of the first layer of insulating material is less than an as-deposited thickness of the first layer of insulating material. The method also includes performing a second deposition process to form a second layer of insulating material on the etched first layer of insulating material, wherein the second layer of insulating material overfills the trench, and removing portions of the etched first layer of insulating material and the second layer of insulating material positioned above the patterned etch mask.

Abstract translation: 在一个示例中，该方法包括在半导体衬底上形成图案化蚀刻掩模，通过图案化蚀刻掩模执行蚀刻工艺，从而在衬底中形成沟槽，执行第一沉积工艺以形成第一层绝缘材料 图案化的蚀刻掩模和在沟槽中，并且对第一绝缘材料层进行蚀刻处理，使得第一绝缘材料层的后蚀刻厚度小于第一绝缘材料层的沉积厚度。 该方法还包括执行第二沉积工艺以在蚀刻的第一绝缘材料层上形成第二绝缘材料层，其中第二绝缘材料层超过沟槽，以及去除蚀刻的第一绝缘材料层的部分和 位于图案化蚀刻掩模上方的第二绝缘材料层。

公开(公告)号：US08455960B2

公开(公告)日：2013-06-04

申请号：US13185112

申请日：2011-07-18

Applicant: Frank Jakubowski ,  Peter Baars ,  Till Schloesser

Inventor： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

IPC: H01L29/00

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

Abstract: Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

Abstract translation: 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

公开(公告)号：US07274060B2

公开(公告)日：2007-09-25

申请号：US11152793

申请日：2005-06-15

Applicant: Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

Inventor： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC: H01L21/8244 ,  H01L29/94

CPC classification number: H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

Abstract: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Abstract translation: 存储单元阵列包括具有存储电容器和存取晶体管的存储单元。 存取晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线上方。

公开(公告)号：US08853051B2

公开(公告)日：2014-10-07

申请号：US13445596

申请日：2012-04-12

Applicant: Frank Jakubowski ,  Jorg Radecker ,  Frank Ludwig

Inventor： Frank Jakubowski ,  Jorg Radecker ,  Frank Ludwig

IPC: H01L21/76

CPC classification number: H01L21/76232 ,  H01L21/76283

Abstract: Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active area in the substrate, forming a patterned masking layer above the substrate, wherein the patterned masking layer exposes the active area and at least a portion of the isolation structure for further processing, and performing a non-selective dry etching process on the exposed active area and the exposed portion of the isolation structure to define a recess in the substrate and to remove at least some of the exposed portions of the isolation structure.

Abstract translation: 通常，本公开涉及在公共蚀刻工艺中凹陷有源区和相邻隔离结构的各种方法。 所公开的一种示例性方法包括在半导体衬底中形成隔离结构，其中隔离结构限定衬底中的有源区，在衬底上形成图案化掩蔽层，其中图案化掩蔽层暴露有源区和至少部分 用于进一步处理的隔离结构，以及在暴露的有源区域和隔离结构的暴露部分上执行非选择性干蚀刻工艺，以限定衬底中的凹部并且去除隔离结构的至少一些暴露部分 。

公开(公告)号：US08716077B2

公开(公告)日：2014-05-06

申请号：US13215635

申请日：2011-08-23

Applicant: Till Schloesser ,  Peter Baars ,  Frank Jakubowski

Inventor： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

IPC: H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848

Abstract: An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

Abstract translation: 一种eDRAM被制造成包括高性能逻辑晶体管技术和超低泄漏DRAM晶体管技术。 实施例包括在衬底中形成凹陷通道，在衬底的上表面的一部分上形成第一栅极氧化物至衬底通道的第一厚度和形成第二厚度的第二栅极氧化物，在凹陷部分中形成第一多晶硅栅极 在所述第二栅极氧化物上形成第二多晶硅栅极，在所述第一和第二多晶硅栅极中的每一个的相对侧上形成间隔物，去除形成第一和第二空腔的第一和第二多晶硅栅极， k电介质层，并且分别在第一和第二空腔中形成第一和第二金属栅极。

公开(公告)号：US08609457B2

公开(公告)日：2013-12-17

申请号：US13099692

申请日：2011-05-03

Applicant: Peter Baars ,  Till Schloesser ,  Frank Jakubowski

Inventor： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

IPC: H01L21/00 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10885

Abstract: Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.

Abstract translation: 通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。 本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。 所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分 的存储器阵列中的导电位线。