公开(公告)号：US07848367B2

公开(公告)日：2010-12-07

申请号：US11896162

申请日：2007-08-30

Applicant: Craig A. Hornbuckle ,  David A. Rowe ,  Thomas W. Krawczyk, Jr. ,  Samuel A. Steidl ,  Inho Kim

Inventor： Craig A. Hornbuckle ,  David A. Rowe ,  Thomas W. Krawczyk, Jr. ,  Samuel A. Steidl ,  Inho Kim

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/047 ,  Y10S370/907

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.

Abstract translation: 公开了高速，高性能，低功率转发器，串行器和解串器。 串行器可以包括serdes成帧器接口（SFI）电路，时钟乘法器单元和复用电路。 解串器可以包括用于接收和调整输入数据信号的输入接收器电路，用于恢复时钟和数据信号的时钟和数据恢复电路（CDR），用于将一个或多个数据信道分成更多数量的数据信道的解复用电路 以及用于产生参考信道并产生要发送到成帧器的输出数据信道的Serdes成帧器接口（SFI）电路。 输入接收机电路可以包括限幅放大器。 串行器和解串器中的每一个还可以包括伪随机模式发生器和错误检查器单元。 串行器和解串器各自可以集成到其相应的半导体芯片中，或者两者可以集成到单个半导体芯片中。

公开(公告)号：US20090074407A1

公开(公告)日：2009-03-19

申请号：US12210152

申请日：2008-09-12

Applicant: Craig A. HORNBUCKLE ,  David A. Rowe

Inventor： Craig A. HORNBUCKLE ,  David A. Rowe

IPC: H04J14/00 ,  H04J3/06

CPC classification number: H04J3/047 ,  H04B10/532 ,  H04B10/5561 ,  H04J3/0691 ,  H04J14/06 ,  H04L27/2067 ,  H04L27/36

Abstract: A communication system includes a multiplexer configured to multiplex a first set of data channels into a first data channel and to multiplex a second set of data channels into a second data channel, and a delay adjuster configured to adjustably delay the first data channel based on a delay adjust command. The communication system also includes a first amplifier configured to amplify the delayed first channel into a first output data channel, and a second amplifier configured to amplify the second data channel into a second output data channel. The communication system further includes a first driver configured to convert the first output data channel into a first drive signal to drive an optical modulator, and a second driver configured to convert the second output data channel into a second drive signal to drive the optical modulator.

Abstract translation: 通信系统包括多路复用器，其被配置为将第一组数据信道多路复用到第一数据信道中，并将第二组数据信道复用到第二数据信道中;以及延迟调整器，被配置为可调节地延迟第一数据信道， 延时调整指令。 通信系统还包括第一放大器，其被配置为将延迟的第一信道放大为第一输出数据信道，以及第二放大器，被配置为将第二数据信道放大为第二输出数据信道。 通信系统还包括配置成将第一输出数据信道转换为第一驱动信号以驱动光调制器的第一驱动器，以及被配置为将第二输出数据信道转换为第二驱动信号以驱动光调制器的第二驱动器。

公开(公告)号：US06937663B2

公开(公告)日：2005-08-30

申请号：US10055007

申请日：2002-01-23

Applicant: Preston Jett ,  Lawrence E. Larson ,  Bret A. Pollack ,  David A. Rowe

Inventor： Preston Jett ,  Lawrence E. Larson ,  Bret A. Pollack ,  David A. Rowe

IPC: H04B1/7163 ,  H04B1/7183 ,  H04B1/719 ,  H04L25/49 ,  H04L27/00

CPC classification number: H04L25/4902 ,  H04B1/71637 ,  H04B1/7183 ,  H04B1/719

Abstract: A baseband signal converter device for an impulse radio receiver combines multiple converter circuits and an RF amplifier in a single integrated circuit package. Each converter circuit includes an integrator circuit that integrates a portion of each RF pulse during a sampling period triggered by a timing pulse generator. The integrator capacitor is isolated by a pair of Schottky diodes connected to a pair of load resistors. A current equalizer circuit equalizes the current flowing through the load resistors when the integrator is not sampling. Current steering logic transfers load current between the diodes and a constant bias circuit depending on whether a sampling pulse is present.

Abstract translation: 用于脉冲无线电接收机的基带信号转换器装置将多个转换器电路和RF放大器组合在单个集成电路封装中。 每个转换器电路包括积分器电路，其在由定时脉冲发生器触发的采样周期期间对每个RF脉冲的一部分进行积分。 积分器电容由一对连接到一对负载电阻的肖特基二极管隔离。 当积分器不采样时，电流均衡器电路均衡流过负载电阻器的电流。 电流转向逻辑根据是否存在采样脉冲，传输二极管之间的负载电流和恒定偏置电路。

公开(公告)号：US06577691B2

公开(公告)日：2003-06-10

申请号：US09910178

申请日：2001-07-20

Applicant: James L. Richards ,  Preston L. Jett ,  Larry W. Fullerton ,  Lawrence E. Larson ,  David A. Rowe

Inventor： James L. Richards ,  Preston L. Jett ,  Larry W. Fullerton ,  Lawrence E. Larson ,  David A. Rowe

IPC: H04L700

CPC classification number: H04B1/7183 ,  G01S7/282 ,  G01S13/0209 ,  G01S13/106 ,  H03L7/18 ,  H04B1/71635 ,  H04L1/08

Abstract: A precision timing generator includes a combiner that provides a timing signal by combining a coarse timing signal and a fine timing signal derived from a phase-shifted sinusoidal signal that has a desired phase shift. The coarse timing generator generates the coarse timing signal from a clock signal and a timing command input. The fine timing generator includes a sinusoidal-signal generator that receives the clock signal and generates a sinusoidal signal. The fine timing generator also includes a phase shifter that receives the sinusoidal signal and the timing command input and shifts the phase of the sinusoidal signal based on the timing input to generate the phase shifted sinusoidal signal.

公开(公告)号：US06304623B1

公开(公告)日：2001-10-16

申请号：US09146524

申请日：1998-09-03

Applicant: James L. Richards ,  Preston Jett ,  Larry W. Fullerton ,  Lawrence E. Larson ,  David A. Rowe

Inventor： James L. Richards ,  Preston Jett ,  Larry W. Fullerton ,  Lawrence E. Larson ,  David A. Rowe

IPC: H04C700

CPC classification number: H03L7/18 ,  H04B1/7163 ,  H04B1/71635 ,  H04B1/7183

Abstract: A frame reference signal is produced as a function of a clock signal. A first timing generator generates a coarse timing signal having a nominal period and a transition occurring at a precise temporal position with respect to the nominal period. The nominal period is a function of the frame reference signal. The temporal position is a function of a first input timing command and the clock signal. A second timing generator generates at least one fine timing transition as a function of a second input timing command and the clock signal. A combiner circuit uses the coarse timing signal to select one of the at least one fine timing transitions to output a precise timing signal, wherein the precise timing signal has a high temporal precision with respect to the frame reference signal.

Abstract translation: 作为时钟信号的函数产生帧参考信号。 第一定时发生器产生具有标称周期和在相对于标称周期的精确时间位置发生的转变的粗定时信号。 标称周期是帧参考信号的函数。 时间位置是第一输入定时命令和时钟信号的函数。 第二定时发生器产生作为第二输入定时命令和时钟信号的函数的至少一个精细定时转换。 组合器电路使用粗定时信号来选择至少一个精细定时转换中的一个以输出精确定时信号，其中精确定时信号相对于帧参考信号具有高的时间精度。

公开(公告)号：US5406847A

公开(公告)日：1995-04-18

申请号：US210085

申请日：1994-03-16

Applicant: David A. Rowe ,  Binneg Y. Lao

Inventor： David A. Rowe ,  Binneg Y. Lao

IPC: G01C19/58 ,  G01P3/44 ,  G01P9/00 ,  G01P15/11

CPC classification number: G01P9/00 ,  G01C19/58 ,  G01P15/11 ,  G01P3/44 ,  Y10S505/843 ,  Y10S505/846

Abstract: A superconducting gyroscope of the present invention includes a circuit which produces a magnetic field which is synchronous with the rate of rotation experienced by the gyroscope, a sensing circuit for converting the synchronous magnetic field into an electric signal, a first shield made of superconducting material for performing shielding of external stray fields, and a second shield disposed inside the first shield and made of superconducting material for expelling trapped residual magnetic flux. The synchronous magnetic field producing circuit includes a magnetic core shaped in a toroid with an air gap. The magnetic core may alternatively be formed in meandering shape by a plurality of separate magnetic core members with a plurality of air gaps therebetween. The sensing circuit includes at least one SQUID which can be directly coupled to the magnetic core. The sensing circuit may also include a superconducting pick-up coil surrounding a portion of the magnetic core for picking up the synchronous magnetic field and producing a London field, and an input coil magnetically coupled to the SQUID. The SQUID and the magnetic core and/or other elements can be fabricated on a single substrate or chip.

Abstract translation: 本发明的超导陀螺仪包括产生与陀螺仪经历的旋转速率同步的磁场的电路，用于将同步磁场转换成电信号的感测电路，由超导材料制成的第一屏蔽 执行外部杂散场的屏蔽，以及设置在第一屏蔽内部并由超导材料制成的用于排出被捕获的残余磁通的第二屏蔽。 同步磁场产生电路包括形成为具有气隙的环形线圈的磁芯。 可选择地，磁芯通过多个分离的磁芯构件以曲折的形状形成，其间具有多个气隙。 感测电路包括至少一个可直接耦合到磁芯的SQUID。 感测电路还可以包括围绕磁芯的一部分的超导拾取线圈，用于拾取同步磁场并产生伦敦场，以及与SQUID磁耦合的输入线圈。 SQUID和磁芯和/或其他元件可以制造在单个衬底或芯片上。

公开(公告)号：US4739448A

公开(公告)日：1988-04-19

申请号：US623990

申请日：1984-06-25

Applicant: David A. Rowe ,  Binneg Y. Lao ,  Robert E. Dietterle

Inventor： David A. Rowe ,  Binneg Y. Lao ,  Robert E. Dietterle

IPC: H01L23/66 ,  H01P3/08 ,  H05K1/02 ,  H05K3/34 ,  H05K7/20

CPC classification number: H01P3/088 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1903 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K3/3431

Abstract: A multilayered integrated circuit chip carrier has a top layer, a signal line layer, a ground layer, a power conductor layer, and a bottom layer with a separating layer between adjacent layers. Each layer has coplanar conductive and dielectric portions, the separating layers being primarily dielectric. The top layer supports an integrated circuit chip and signal launcher pads on the bottom layer couple signal and power lines of a printed circuit board to spaced points about the bottom layer periphery and substantially constant signal line impedance is achieved. The signal line layer is separated from the power conductor layer by a ground plane layer. Conductive via through pads are placed in the separating layers to form a plurality of separate conductive paths from each of the bottom and top layers to each of the signal line and power conductor layers. Via through pads are also placed in the separating layers to break up cavities and thus increase cavity resonance above signal frequencies and are placed in the signal line layer to provide signal line isolation. Thermal columns of via pads in the separating layers and conductive portions in the other layers under the chip provide chip cooling. Large grounded conductive areas in the top and bottom layers reduce unwanted signal coupling to the external environment. A capacitive coupling on the top layer between a power conductor and ground provides power line isolation.

Abstract translation: 多层集成电路芯片载体具有顶层，信号线层，接地层，电源导体层和在相邻层之间具有分离层的底层。 每个层具有共面的导电和电介质部分，分离层主要是电介质。 顶层支持集成电路芯片，底层上的信号发射器焊盘将印刷电路板的信号和电力线耦合到围绕底层外围的间隔点，并实现基本恒定的信号线阻抗。 信号线层通过接地层与电源导体层分离。 导电通孔通过焊盘放置在分离层中以形成从底层和顶层中的每一层到信号线和电源导体层中的每一个的多个单独的导电路径。 通孔焊盘也放置在分离层中以分解空腔，从而增加信号频率以上的空腔谐振，并放置在信号线层中以提供信号线隔离。 分离层中的通孔焊盘的热柱和芯片下的其它层中的导电部分提供芯片冷却。 顶部和底部的大的接地导电区域减少了与外部环境的不必要的信号耦合。 电源导体和地之间的顶层电容耦合提供电源线隔离。

公开(公告)号：US07965988B2

公开(公告)日：2011-06-21

申请号：US12575458

申请日：2009-10-07

Applicant: Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

Inventor： Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

IPC: H04B1/38 ,  H04K3/00

CPC classification number: H04B17/14 ,  H04B7/08 ,  H04B17/101 ,  H04B17/104

Abstract: An example of a method for off-line calibration of a radio frequency (RF) communication system may include one or more of the following: enabling an off-line calibration mode for an RF communication system; generating an off-line calibration signal; applying to a frequency converter a first off-line calibration signal corresponding to the generated off-line calibration signal; translating the first off-line calibration signal into a second off-line calibration signal; evaluating one or more calibration adjustment signals associated with the calibration signal to reduce error in the communication system, wherein the one or more calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances; storing one or more calibration adjustment signals; disabling the off-line calibration mode; applying a communication signal; and adjusting the communication signal based on the stored one or more calibration adjustment signals.

Abstract translation: 用于射频（RF）通信系统的离线校准的方法的示例可以包括以下中的一个或多个：启用用于RF通信系统的离线校准模式; 产生离线校准信号; 向频率转换器施加对应于所生成的离线校准信号的第一离线校准信号; 将所述第一离线校准信号转换为第二离线校准信号; 评估与所述校准信号相关联的一个或多个校准调节信号以减少所述通信系统中的误差，其中所述一个或多个校准调整信号可以包括与DC偏移相关联的偏移参数和与增益和相位中的至少一个相关联的不平衡参数 不平衡 存储一个或多个校准调整信号; 禁用离线校准模式; 应用通信信号; 以及基于所存储的一个或多个校准调整信号来调整通信信号。

公开(公告)号：US20100022199A1

公开(公告)日：2010-01-28

申请号：US12575457

申请日：2009-10-07

Applicant: Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

Inventor： Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

IPC: H04B1/40

CPC classification number: H04B17/14 ,  H04B7/08 ,  H04B17/101 ,  H04B17/104

Abstract: An example of a radio frequency (RF) receiver system for communication may include a receive channel frequency converter configured to provide a second receive calibration signal during a receive calibration mode based on a first receive calibration signal and a receive reference signal. The system may include a receive pre-distortion module coupled to the receive channel frequency converter. The receive pre-distortion module may be configured to provide a fourth receive calibration signal during the receive calibration mode based on a third receive calibration signal and one or more receive calibration adjustment signals. The one or more receive calibration adjustment signals may comprise an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances.

Abstract translation: 用于通信的射频（RF）接收机系统的示例可以包括接收信道频率转换器，其被配置为在基于第一接收校准信号和接收参考信号的接收校准模式期间提供第二接收校准信号。 该系统可以包括耦合到接收信道频率转换器的接收预失真模块。 接收预失真模块可以被配置为在接收校准模式期间基于第三接收校准信号和一个或多个接收校准调整信号来提供第四接收校准信号。 一个或多个接收校准调整信号可以包括与DC偏移相关联的偏移参数和与增益和相位不平衡中的至少一个相关联的不平衡参数。

公开(公告)号：US20070298733A1

公开(公告)日：2007-12-27

申请号：US11590278

申请日：2006-10-30

Applicant: Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

Inventor： Jean-Pierre Joseph Cole ,  David A. Rowe ,  Craig A. Hornbuckle

IPC: H04B1/04

CPC classification number: H04B17/14 ,  H04B7/08 ,  H04B17/101 ,  H04B17/104

Abstract: A radio frequency transceiver for off-line transmit and receive calibrations includes: a transmit pre-distortion module configured to receive a transmit calibration signal during a transmit calibration mode, a transmit communication signal during a transmit communication operation mode, and one or more transmit calibration adjustment signals; a transmit channel frequency converter; and a transmit calibration module configured to provide the one or more transmit calibration adjustment signals and the transmit calibration signal to the transmit pre-distortion module. It may also include a receive channel frequency converter; a receive pre-distortion module configured to receive a receive calibration signal during the receive calibration mode, a receive communication signal during a receive communication operation mode, and one or more receive calibration adjustment signals; and a receive calibration module configured to provide the one or more receive calibration adjustment signals to the receive pre-distortion module and a receive calibration signal to the transmit pre-distortion module.

Abstract translation: 用于离线发射和接收校准的射频收发器包括：发射预失真模块，被配置为在发射校准模式期间接收发射校准信号，在发射通信操作模式期间接收发射校准信号，以及一个或多个发射校准 调整信号; 发射信道变频器; 以及发射校准模块，被配置为将所述一个或多个发射校准调整信号和所述发射校准信号提供给所述发射预失真模块。 它还可以包括接收频道变频器; 接收预失真模块，被配置为在接收校准模式期间接收接收校准信号，接收通信操作模式期间的接收通信信号以及一个或多个接收校准调整信号; 以及接收校准模块，其被配置为向所述接收预失真模块提供所述一个或多个接收校准调整信号，以及向所述发射预失真模块提供接收校准信号。