Circuit for preventing latch-up in DC-DC converter
    11.
    发明授权
    Circuit for preventing latch-up in DC-DC converter 有权
    用于防止DC-DC转换器闭锁的电路

    公开(公告)号:US07385434B2

    公开(公告)日:2008-06-10

    申请号:US11321952

    申请日:2005-12-28

    Applicant: Chung-Heon Lee

    Inventor: Chung-Heon Lee

    CPC classification number: H02M3/07 H02M2001/008 H02M2003/078

    Abstract: There is provided a circuit for preventing latch-up in a DC-DC. The circuit for preventing a latch-up phenomenon in a DC-DC converter, the DC-DC converter having a first and a second DC-DC converters coupled with each other in one chip for receiving an input voltage to generate a positive voltage and a negative voltage, respectively, in which a parasitic block with a PNP transistor and an NPN transistor causing a latch-up phenomenon is embedded, the circuit includes a first pathway for controlling an input current flowing to the first DC-DC converter from an input terminal receiving the input voltage in order that the PNP transistor is turned on and the NPN transistor is not turned on; and a second pathway for supplying the input current to the first DC-DC converter intactly at a timing that both the positive and negative voltages reach target voltages.

    Abstract translation: 提供了用于防止DC-DC中的闩锁的电路。 用于防止DC-DC转换器中的闩锁现象的电路,DC-DC转换器具有在一个芯片中彼此耦合的第一和第二DC-DC转换器,用于接收输入电压以产生正电压,以及 负电压,其中埋入具有PNP晶体管和NPN晶体管的引起闭锁现象的寄生块,该电路包括用于从输入端子控制流向第一DC-DC转换器的输入电流的第一路径 接收输入电压以使PNP晶体管导通,并且NPN晶体管不导通; 以及用于在正负电压达到目标电压的定时将输入电流提供给第一DC-DC转换器的第二路径。

    Circuit for preventing latch-up in DC-DC converter
    14.
    发明申请
    Circuit for preventing latch-up in DC-DC converter 有权
    用于防止DC-DC转换器闭锁的电路

    公开(公告)号:US20060145671A1

    公开(公告)日:2006-07-06

    申请号:US11321952

    申请日:2005-12-28

    Applicant: Chung-Heon Lee

    Inventor: Chung-Heon Lee

    CPC classification number: H02M3/07 H02M2001/008 H02M2003/078

    Abstract: There is provided a circuit for preventing latch-up in a DC-DC. The circuit for preventing a latch-up phenomenon in a DC-DC converter, the DC-DC converter having a first and a second DC-DC converters coupled with each other in one chip for receiving an input voltage to generate a positive voltage and a negative voltage, respectively, in which a parasitic block with a PNP transistor and an NPN transistor causing a latch-up phenomenon is embedded, the circuit includes a first pathway for controlling an input current flowing to the first DC-DC converter from an input terminal receiving the input voltage in order that the PNP transistor is turned on and the NPN transistor is not turned on; and a second pathway for supplying the input current to the first DC-DC converter intactly at a timing that both the positive and negative voltages reach target voltages.

    Abstract translation: 提供了用于防止DC-DC中的闩锁的电路。 用于防止DC-DC转换器中的闩锁现象的电路,DC-DC转换器具有在一个芯片中彼此耦合的第一和第二DC-DC转换器,用于接收输入电压以产生正电压,以及 负电压,其中埋入具有PNP晶体管和NPN晶体管的引起闭锁现象的寄生块,该电路包括用于从输入端子控制流向第一DC-DC转换器的输入电流的第一路径 接收输入电压以使PNP晶体管导通,并且NPN晶体管不导通; 以及用于在正负电压达到目标电压的定时将输入电流提供给第一DC-DC转换器的第二路径。

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