公开(公告)号：US20210063655A1

公开(公告)日：2021-03-04

申请号：US16559979

申请日：2019-09-04

Applicant: GLOBALFOUNDRIES Inc. ,  KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Sujith Chandran ,  Marcus Dahlem ,  Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  Bruna Paredes ,  Jaime Viegas

IPC: G02B6/42 ,  G02B6/293

Abstract: Structures for a wavelength-division multiplexing filter and methods of fabricating a structure for a wavelength-division multiplexing filter. The structure includes a first waveguide core, a second waveguide core laterally spaced from the first waveguide core, and a ring resonator arranged in a vertical direction over the first waveguide core and the second waveguide core. The ring resonator is also arranged in a lateral direction between the first waveguide core and the second waveguide core. The first and second waveguide cores are composed of a semiconductor material, such as single-crystal silicon, and the ring resonator is composed of a dielectric material, such as silicon nitride.

公开(公告)号：US10937685B2

公开(公告)日：2021-03-02

申请号：US16446588

申请日：2019-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Haiting Wang ,  Jiehui Shu

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.

公开(公告)号：US20210057558A1

公开(公告)日：2021-02-25

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US20210055478A1

公开(公告)日：2021-02-25

申请号：US16549197

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/122 ,  G02B6/30 ,  G02B6/136

Abstract: Structures for a waveguide coupler and methods of fabricating a structure for a waveguide coupler. A first waveguide core has a first width, a second waveguide core has a second width less than the first width, and a waveguide coupler includes first and second tapers that are positioned between the first waveguide core and the second waveguide core. The second taper is directly connected with the first taper, and the first and second tapers connect the first and second waveguide cores.

公开(公告)号：US10930777B2

公开(公告)日：2021-02-23

申请号：US15819825

申请日：2017-11-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ignasi Cortes Mayol ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

公开(公告)号：US20210050419A1

公开(公告)日：2021-02-18

申请号：US16541600

申请日：2019-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US20210050412A1

公开(公告)日：2021-02-18

申请号：US16538785

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Haiting Wang ,  Yong Jun Shi ,  Xiaoming Yang ,  Liu Jiang

IPC: H01L29/06 ,  H01L23/66 ,  H01L21/764 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

公开(公告)号：US10923388B2

公开(公告)日：2021-02-16

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Yuping Ren ,  Paul Ackmann ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US20210043727A1

公开(公告)日：2021-02-11

申请号：US16534317

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US10896853B2

公开(公告)日：2021-01-19

申请号：US16396775

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Rinus Tek Po Lee ,  Wei Hong ,  Hui Zang ,  Hong Yu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.