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161.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为4/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20160241271A1
公开(公告)日：2016-08-18
申请号：US14719254
申请日：2015-05-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2767 , H03M13/1105 , H04L1/0041 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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162.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为4/15和256符号映射，以及使用相同的位交互方法公开(公告)号：US20160241269A1
公开(公告)日：2016-08-18
申请号：US14718839
申请日：2015-05-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于256符号映射的调制器。
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163.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为2/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20160218746A1
公开(公告)日：2016-07-28
申请号：US14718013
申请日：2015-05-20
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2767 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/2792 , H04L1/0057 , H04L1/0071 , H04L2001/0093
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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164.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 有权低密度奇偶校验编码器的长度为64800，编码速率为2/15，低密度奇偶校验编码方法使用该编码方法公开(公告)号：US20160049957A1
公开(公告)日：2016-02-18
申请号：US14496457
申请日：2014-09-25
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800，码率为2/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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165.发明申请METHOD AND APPARATUS FOR TRANSMITTING/RECEIVING BROADCASTING-COMMUNICATION DATA 有权用于发送/接收广播通信数据的方法和装置公开(公告)号：US20140153615A1
公开(公告)日：2014-06-05
申请号：US14174622
申请日：2014-02-06
Inventor： Sung-Ik PARK , Hyoungsoo LIM , Heung-Mook KIM , Soo-In LEE
CPC classification number: H04H40/18 , H04B1/709 , H04L1/0041 , H04L1/0047 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L2001/0093 , H04W52/322
Abstract: A broadcasting-communication data receiving apparatus for receiving mixed signals including original signals and additional signals. The apparatus includes a receiver for receiving the mixed signals and outputting mixed signals of a predetermined band, a first demodulator for receiving the mixed signals of the predetermined band and generating baseband mixed signals, an original data generator for receiving the baseband mixed signals and generating original data, an original signal generator for receiving the original data and generating baseband original signals, a modulator for receiving the baseband original signals and generating original signals of a predetermined band, a subtractor for subtracting the original and mixed signals of the predetermined band to thereby generate additional signals of a predetermined band, a second demodulator for receiving the additional signals of the predetermined band and generating baseband additional signals, and an additional data generator for receiving the baseband additional signals and generating additional data.
Abstract translation: 一种用于接收包括原始信号和附加信号的混合信号的广播通信数据接收装置。 该装置包括用于接收混合信号并输出预定频带的混合信号的接收机，用于接收预定频带的混合信号并产生基带混合信号的第一解调器，用于接收基带混合信号并产生原始数据的原始数据发生器 数据，用于接收原始数据并产生基带原始信号的原始信号发生器，用于接收基带原始信号并产生预定频带的原始信号的调制器，用于减去预定频带的原始信号和混合信号的减法器，从而产生 预定频带的附加信号，用于接收预定频带的附加信号并产生基带附加信号的第二解调器，以及用于接收基带附加信号并产生附加数据的附加数据发生器。
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Patent Agency Ranking
166.发明申请公开(公告)号：US20250039933A1
公开(公告)日：2025-01-30
申请号：US18785859
申请日：2024-07-26
Inventor： Jung Sun UM , Hoi Yoon JUNG , Sung-Ik PARK , Nam Ho HUR
IPC: H04W74/0816 , H04L27/26 , H04W74/08 , H04W92/18
Abstract: A method of a first terminal may comprise: receiving a higher layer message including basic sidelink synchronization signal block (S-SSB) information on a basic S-SSB transmitted in an unlicensed band; obtaining a channel occupancy time (COT) through a listen-before-talk (LBT) procedure in the unlicensed band; and transmitting COT information including additional S-SSB configuration information to other terminals, wherein the basic S-SSB information includes information on a transmission occasion of the basic S-SSB and information on a frequency of the basic S-SSB, and the additional S-SSB configuration information includes information for transmission of an additional S-SSB that is transmitted in addition to the basic S-SSB within the COT.
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167.发明公开公开(公告)号：US20230378978A1
公开(公告)日：2023-11-23
申请号：US18364421
申请日：2023-08-02
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/2792 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0071 , H03M13/255 , H03M13/616 , H04L27/3422 , H03M13/1105 , H04L1/0057
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
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公开(公告)号：US20230318679A1
公开(公告)日：2023-10-05
申请号：US18190421
申请日：2023-03-27
Inventor： Jung-Sun UM , Sung-Ik PARK , Hoi-Yoon JUNG , Dong-Joon CHOI , Nam-Ho HUR
IPC: H04B7/06
CPC classification number: H04B7/0669 , H04B7/0697 , H04B7/068
Abstract: Disclosed herein is a method for signal configuration. The method may include evenly dividing, by a signal-bit configuration block, data or information forming signal bits or a signal bitstring and transferring the same to N multiple channels; mapping, by a first spatial path configuration block, a coded bitstring, which is generated through coding and signal processing of the data or information forming the signal bits or the signal bitstring, to cells corresponding to M antennas; and configuring, by a frequency path configuration block, the transmission paths of the cells.
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169.发明公开公开(公告)号：US20230318625A1
公开(公告)日：2023-10-05
申请号：US18330955
申请日：2023-06-07
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1157 , H03M13/1165 , H03M13/036 , H03M13/1185 , H03M13/616 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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170.发明公开公开(公告)号：US20230275600A1
公开(公告)日：2023-08-31
申请号：US18314938
申请日：2023-05-10
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
CPC classification number: H03M13/152 , H03M13/116 , H03M13/1162 , H03M13/1165 , H03M13/271 , H03M13/2778 , H03M13/618 , H03M13/6362 , H03M13/253
Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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