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    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    133.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250151629A1

    公开(公告)日：2025-05-08

    申请号：US18799264

    申请日：2024-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungjong JEONG

    IPC: H10N50/10 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

    Abstract: A magnetoresistive random access memory device may include a wiring structure on a substrate, an etch stop layer on the wiring structure, an interlayer insulation layer on the etch stop layer, a plurality of contact structures penetrating the interlayer insulation layer and the etch stop layer to contact the wiring structure, each of the plurality of contact structures including a first portion having a sidewall facing the interlayer insulation layer and a second portion having a sidewall facing the etch stop layer, and a plurality of magnetic tunnel junction structures on the plurality of contact structures and connected to corresponding ones of the plurality of contact structures, respectively, wherein a first width of the first portion in a first horizontal direction is greater than a second width of the second portion in the first horizontal direction.

    IMAGE SENSOR
    136.
    发明申请
    IMAGE SENSOR 有权

    公开(公告)号：US20250151445A1

    公开(公告)日：2025-05-08

    申请号：US18742302

    申请日：2024-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ingyu BAEK ,  Jinmyoung LEE ,  Soonhyung HONG

    IPC: H01L27/146

    Abstract: An image sensor that includes a first layer and a second layer bonded to the first layer. The first layer includes a first substrate including a first front surface and a first back surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad. The second layer includes a second substrate including a second front surface and a second back surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between one of the pixel transistors and the second pad. The second conductive line passes through the second substrate and is electrically connected to a lower portion of the pixel transistor.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    138.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250151304A1

    公开(公告)日：2025-05-08

    申请号：US19009795

    申请日：2025-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

    IPC: H10D30/01 ,  H10D30/62 ,  H10D84/01 ,  H10D84/03

    Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

    MEMORY DEVICE HAVING COP STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME
    139.
    发明申请
    MEMORY DEVICE HAVING COP STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20250151292A1

    公开(公告)日：2025-05-08

    申请号：US18732795

    申请日：2024-06-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyoung Lee ,  Keonwoo Park ,  Hyunchul Yoon

    IPC: H10B80/00 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of wordlines and a plurality of bitlines, and includes a plurality of normal memory cells storing normal data and a plurality of error correction code (ECC) memory cells storing ECC data. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit. The peripheral circuit controls the memory cell array, and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are disposed in the first semiconductor layer and at least a portion of a region in which the row decoder is disposed in the second semiconductor layer overlap in a plan view.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    140.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250151279A1

    公开(公告)日：2025-05-08

    申请号：US18668971

    申请日：2024-05-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNHYOUNG KIM ,  JIYOUNG KIM ,  IK-HYUNG JOO ,  SUKKANG SUNG ,  SEHOON LEE

    IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor disposed on the semiconductor substrate. The first transistor includes an insulation structure disposed on the semiconductor substrate, a channel region disposed on the insulation structure and including a first semiconductor layer, and extending in a direction crossing the semiconductor substrate, first source and drain regions electrically connected to the channel region, a first gate insulating layer disposed on the channel region, and a first gate electrode disposed on the first gate insulating layer. A first region that is one of the first source and drain regions and a second region that is another one of the first source and drain regions include different materials or have different crystal structures.

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