公开(公告)号：US5450570A

公开(公告)日：1995-09-12

申请号：US158147

申请日：1993-11-24

Applicant: Martin D. Richek ,  Robert S. Gready ,  Curtis R. Jones ,  Jeffrey S. Perry

Inventor： Martin D. Richek ,  Robert S. Gready ,  Curtis R. Jones ,  Jeffrey S. Perry

IPC: G06F9/445 ,  G06F15/177 ,  G06F13/00

CPC classification number: G06F9/4411 ,  G06F15/177

Abstract: An method and apparatus for determining and selecting configuration options and settings of circuit boards used in a computer system. The options and settings are placed in a file according to a given format, at which time the system determines if non-conflicting use of the common system resources is possible. The method and apparatus also provide for definable linking resources which further define relationships between various boards within a computer system and the allocation of common computer resources to the circuit boards. The method also decreases the time required for the computer to resolve linking resource and common computer resource allocation conflicts by processing only those resource requirements required to resolve the conflict.

Abstract translation: 一种用于确定和选择在计算机系统中使用的电路板的配置选项和设置的方法和装置。 选项和设置根据给定的格式放置在一个文件中，此时系统确定是否可以使用公共系统资源的非冲突使用。 该方法和装置还提供可定义的链接资源，其进一步限定计算机系统内的各个板之间的关系以及将公共计算机资源分配给电路板。 该方法还减少了计算机通过仅处理解决冲突所需的资源要求来解决链接资源和公共计算机资源分配冲突所需的时间。

公开(公告)号：US5434997A

公开(公告)日：1995-07-18

申请号：US955980

申请日：1992-10-02

Applicant: John A. Landry ,  Jeff W. Wolford ,  Walter G. Fry ,  Roger E. Tipley

Inventor： John A. Landry ,  Jeff W. Wolford ,  Walter G. Fry ,  Roger E. Tipley

IPC: G06F11/16 ,  G06F11/00 ,  G06F17/30

CPC classification number: G06F11/1637 ,  G06F11/1679

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Abstract translation: 一种用于在计算机系统中操作紧耦合的镜像处理器的方法和装置。 多个CPU板耦合到通常称为主机总线的处理器/存储器总线。 每个CPU板包括一个处理器以及各个处理器本地的各种端口，定时器和中断控制器逻辑。 一个或多个CPU板上的处理器被指定为主处理器，其余CPU板上的处理器被指定为镜像或从属处理器。 主处理器具有对主机总线的完全访问和用于读和写周期的第二复用总线，而从处理器被阻止写入任何总线。 从处理器将写入数据和各种控制信号与其相应的主处理器产生的差异进行比较。 该系统包括中断控制器同步逻辑，以同步中断请求以及定时器同步逻辑，以同步每个主CPU和从CPU的定时器，以保证主CPU和从CPU处于锁定状态。

公开(公告)号：US5408636A

公开(公告)日：1995-04-18

申请号：US255233

申请日：1994-06-07

Applicant: Paul Santeler ,  Gary W. Thome ,  Roger E. Tipley

Inventor： Paul Santeler ,  Gary W. Thome ,  Roger E. Tipley

IPC: G06F12/08 ,  G06F13/12

CPC classification number: G06F12/0888 ,  G06F12/0891 ,  G06F12/0897

Abstract: A computer system that flushes an internal cache in the microprocessor and an external cache to insure cache coherency. The computer system will flush the caches when a write command is directed to those specific portions that are write protected. The microprocessor is placed in a hold state before the flushing process is initiated. The cache memories are then cleared. Thus the microprocessor will not be able to read the incoherent information stored in the cache and yet data obtained during read operations can be cached for performance increase.

Abstract translation: 刷新微处理器内部高速缓存和外部缓存以确保高速缓存一致性的计算机系统。 当写入命令指向写保护的特定部分时，计算机系统将刷新缓存。 在启动冲洗过程之前，微处理器处于保持状态。 然后清除高速缓存。 因此，微处理器将无法读取存储在高速缓存中的非相干信息，并且可以缓存读取操作期间获得的数据以提高性能。

公开(公告)号：US5325535A

公开(公告)日：1994-06-28

申请号：US719182

申请日：1991-06-21

Applicant: Paul Santeler ,  Gary W. Thome

Inventor： Paul Santeler ,  Gary W. Thome

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/36 ,  G06F13/4239

Abstract: An apparatus which receives locking signals from a first device and provides a lengthened version of certain of these signals to a second device. The apparatus stretches the locking signal provided to ensure that the signal remains valid throughout the entire locked sequence. The apparatus also indicates when arbitration windows are available between back-to-back locked cycles, i.e. when it is okay to relinquish control of the host bus to a requesting bus master or device. The apparatus monitors cache controller activity and notifies arbitration logic when the last write cycle of a read-modify-write sequence or multiple transfer write cycle begins. When the cycle completes, the arbitration logic releases the bus, thus providing an arbitration window for other requesting bus masters and devices. In this manner, overlock conditions which block bus masters from obtaining control of the bus are prevented from occurring.

Abstract translation: 一种从第一设备接收锁定信号并将这些信号中的某些信号的延长版本提供给第二设备的设备。 设备延伸提供的锁定信号，以确保信号在整个锁定序列中保持有效。 该装置还指示在背靠背锁定周期之间的仲裁窗口可用时，即当将主机总线的控制放弃到请求总线主机或设备是可行的。 当读 - 修改 - 写入序列或多个传输写周期的最后一个写周期开始时，该设备监视高速缓存控制器活动并通知仲裁逻辑。 当循环完成时，仲裁逻辑释放总线，从而为其他请求总线主机和设备提供仲裁窗口。 以这种方式，防止阻止总线主机获得总线控制的封锁条件发生。

公开(公告)号：US5315228A

公开(公告)日：1994-05-24

申请号：US825638

申请日：1992-01-24

Applicant: Randall L. Hess ,  Patrick R. Cooper ,  Armando Interiano ,  Joseph F. Freiman

Inventor： Randall L. Hess ,  Patrick R. Cooper ,  Armando Interiano ,  Joseph F. Freiman

IPC: G01R31/00 ,  G01R31/36 ,  H02J7/00 ,  H02J7/04

CPC classification number: G01R31/3648 ,  G01R19/16542 ,  G01R31/006 ,  G01R31/361 ,  G01R31/3624 ,  G01R31/3655

Abstract: A battery charge controller and fuel gauge which accurately monitors the voltage, temperature, and charge and discharge current of a rechargeable battery, and calculates the battery's charge capacity and charge level. Each time the battery is fully discharged, any calculated charge level remaining is divided by two and subtracted from the previously calculated charge capacity. When the battery is fully charged, the charge level is set equal to the charge capacity. During subsequent charge and discharge, the current is converted to a coulomb count and added or subtracted from the charge level to maintain an accurate charge level. Fast charge inefficiency due to temperature is considered by subtracting a temperature proportional factor before the charge level of the battery is updated. The charge level, voltage and temperature are used to determine the optimal fast charge termination point to achieve full charge and prevent temperature abuse and overcharge. A fast charge is applied only if the battery is within proper voltage and temperature ranges. The charge controller includes a microcontroller circuit within the same battery pack as the battery, which is powered by the battery when AC power is unavailable. The microcontroller circuit consumes very little power, measures circuit errors to assure data accuracy, times periods of self-discharge and updates the charge level accordingly. The microcontroller circuit also includes memory to store the battery charge information and a communication port to provide the charge information to a computer system connected to the battery pack.

Abstract translation: 电池充电控制器和电量计，可精确监测充电电池的电压，温度和充放电电流，并计算电池的充电容量和充电电量。 每次电池完全放电时，剩余的任何计算的电荷水平除以2，并从先前计算的充电容量中减去。 当电池充满电时，充电电平设置为等于充电容量。 在随后的充电和放电期间，电流被转换为库仑计数，并从充电电平加减，以保持精确的充电电平。 通过在更新电池的充电水平之前减去温度比例因子来考虑由于温度导致的快速充电效率低下。 充电电平，电压和温度用于确定最佳快速充电终止点以实现充满电并防止温度滥用和过充电。 仅当电池在适当的电压和温度范围内时，才能使用快速充电。 充电控制器包括与电池相同的电池组中的微控制器电路，当电力不可用时，它由电池供电。 微控制器电路消耗很少的功率，测量电路误差以确保数据精度，自放电的时间周期和相应的电荷电平更新。 微控制器电路还包括用于存储电池电荷信息的存储器和通信端口，以向连接到电池组的计算机系统提供充电信息。

公开(公告)号：US5283880A

公开(公告)日：1994-02-01

申请号：US636732

申请日：1991-01-02

Applicant: Fernando Marcias-Garza

Inventor： Fernando Marcias-Garza

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0215 ,  G06F12/0802

Abstract: A method for performing buffer copy operations in a personal computer system utilizing paged memory mode architecture and having a cache memory. The contents of a first buffer are read into a microprocessor register and simultaneously written into a cache memory. The first buffer is then read again and written to a second buffer, with the actual data values being obtained from the cache memory. This method avoids excessive wait states associated with changing memory pages from the first buffer memory address to the second buffer memory address for each data value.

Abstract translation: 一种用于在个人计算机系统中执行缓冲器复制操作的方法，该系统利用分页存储器模式架构并具有高速缓冲存储器。 将第一缓冲器的内容读入微处理器寄存器并同时写入高速缓冲存储器。 然后再次读取第一缓冲区并将其写入第二缓冲器，其中实际的数据值是从高速缓冲存储器获得的。 该方法避免了与针对每个数据值从第一缓冲存储器地址改变到第二缓冲存储器地址的存储器页面相关联的过多等待状态。

公开(公告)号：US5247685A

公开(公告)日：1993-09-21

申请号：US996526

申请日：1992-12-23

Applicant: John A. Landry ,  Paul R. Culley

Inventor： John A. Landry ,  Paul R. Culley

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

Abstract translation: 两个独立运行的微处理器共享共同的控制，数据和地址总线。 当总线上的第一个微处理器在总线上被分配时，通过在下一个总线周期开始时将中断向量放置在总线上来响应所有可屏蔽的中断。 当第二个微处理器在总线上并且接收到可屏蔽中断时，禁止下一个总线周期的开始，使中断向量放在总线上。

公开(公告)号：US5178318A

公开(公告)日：1993-01-12

申请号：US711331

申请日：1991-06-06

Applicant: Eric R. Edwin ,  James J. Tumlinson ,  Jerome A. Wilson ,  Thad C. McMillan, Jr. ,  Rollin G. Meyer ,  Darryl J. McKenney

Inventor： Eric R. Edwin ,  James J. Tumlinson ,  Jerome A. Wilson ,  Thad C. McMillan, Jr. ,  Rollin G. Meyer ,  Darryl J. McKenney

IPC: H05K1/03 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K3/4691 ,  H05K3/3452 ,  H05K1/0366 ,  H05K2201/0909 ,  H05K2203/0557 ,  H05K2203/308 ,  H05K3/341

Abstract: A rigid-flex printed circuit board having a rigid section and a flexible section extending from the rigid section is disclosed. The rigid-flex printed circuit board is capable of withstanding high temperatures experienced in high volume production environments utilizing infrared reflow ovens by providing spacers and covers for protecting the flexible section from high temperatures. A process for assembling components and devices on the rigid-flex printed circuit board in a high volume production environment utilizing infrared reflow ovens is also disclosed.

公开(公告)号：US5001604A

公开(公告)日：1991-03-19

申请号：US427753

申请日：1989-10-26

Applicant: W. Randolph Lusby

Inventor： W. Randolph Lusby

IPC: G01R31/28 ,  H01K3/06 ,  H01R12/04 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K3/4691 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An improved structure for testing the operability of a completed circuit board having components thereon and improved method of fabricating same are disclosed. The structure and process include the use of an insulator portion with a printed circuit board adhered thereto which includes a testing pattern to evaluate the operability of a completed printed circuit board. The insulator portion which provides support for the test pattern extends past the edge of the printed circuit board thereby permitting one to test the operability of the printed circuit board without having to utilize valuable space and contact points on the printed board itself to test the operability of the completed printed circuit board once components have been installed.

公开(公告)号：US4933832A

公开(公告)日：1990-06-12

申请号：US365099

申请日：1989-06-12

Applicant: Michael E. Schneider ,  Richard A. Faulk

Inventor： Michael E. Schneider ,  Richard A. Faulk

IPC: H02M1/10

CPC classification number: H02M1/10

Abstract: An automatic line monitor for use in conjunction with a power supply for electronic components automatically accommodates either of two voltage ranges. Since the power supply may operate in domestic voltage ranges of about 100 volts or in international voltage ranges of about 120, the automatic line monitor senses and automatically switches to a voltage-doubling mode for the domestic range or a non-voltage-doubling mode for the higher international range. A latch may latch the line monitor in a non-voltage doubling mode once the higher voltage range is sensed. A monitor of a preferred embodiment eliminates almost all of the high-power-handling elements of the switch so that almost all of the operative elements of the switch may be incorporated on a single integrated circuit chip.

Abstract translation: 与电子部件的电源一起使用的自动线路监视器自动适应两个电压范围中的任一个。 由于电源可以在约100伏的国内电压范围内或在约120的国际电压范围内工作，所以自动线路监视器感测并自动切换到家用范围的电压倍增模式或非电压倍增模式 国际范围较高。 一旦检测到较高的电压范围，锁存器就可以将线路监视器锁定在非电压倍增模式中。 优选实施例的监视器消除了开关的几乎所有高功率处理元件，使得开关的几乎所有的操作元件可以并入单个集成电路芯片。