公开(公告)号：US20210296313A1

公开(公告)日：2021-09-23

申请号：US17131542

申请日：2020-12-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Kuo-Cheng Ching

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78

摘要： Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

公开(公告)号：US20210280694A1

公开(公告)日：2021-09-09

申请号：US17322267

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

摘要： A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US11114566B2

公开(公告)日：2021-09-07

申请号：US16033256

申请日：2018-07-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zhi-Chang Lin ,  Kai-Chieh Yang ,  Chia-Wei Su ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Chih-Hao Wang

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/302 ,  H01L23/532 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

摘要： A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

公开(公告)号：US11031489B2

公开(公告)日：2021-06-08

申请号：US16142672

申请日：2018-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

摘要： A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

公开(公告)号：US11011625B2

公开(公告)日：2021-05-18

申请号：US16510554

申请日：2019-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

摘要： A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20210066294A1

公开(公告)日：2021-03-04

申请号：US16932476

申请日：2020-07-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US10825918B2

公开(公告)日：2020-11-03

申请号：US16260483

申请日：2019-01-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi-Ning Ju

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/088

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.

公开(公告)号：US20200098758A1

公开(公告)日：2020-03-26

申请号：US16279824

申请日：2019-02-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu

IPC分类号： H01L27/092 ,  H01L27/02 ,  H01L27/11 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66

摘要： A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

公开(公告)号：US20200098622A1

公开(公告)日：2020-03-26

申请号：US16510554

申请日：2019-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20200006531A1

公开(公告)日：2020-01-02

申请号：US16544196

申请日：2019-08-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/768

摘要： A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.