公开(公告)号：US10417734B2

公开(公告)日：2019-09-17

申请号：US15698217

申请日：2017-09-07

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US20190272615A1

公开(公告)日：2019-09-05

申请号：US16417899

申请日：2019-05-21

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Akif Ali

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06T1/60 ,  G06T11/00 ,  G06F15/08

Abstract: One embodiment provides for a processor comprising a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores and interconnect logic to interconnect the graphics processor cores of the 3D integrated circuit stack to enable data distribution between the graphics processor cores over a virtual channel including multiple programmatically pre-assigned traffic classifications.

公开(公告)号：US10403003B2

公开(公告)日：2019-09-03

申请号：US15494812

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Farshad Akhbari

IPC: G06T9/00

Abstract: An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10373285B2

公开(公告)日：2019-08-06

申请号：US15482810

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US20190213707A1

公开(公告)日：2019-07-11

申请号：US15867688

申请日：2018-01-10

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Nicolas Kacevas ,  Altug Koker ,  Parth Damani ,  Satyanarayana Nekkalapu

IPC: G06T1/60 ,  G06F12/1027 ,  G06F12/1009 ,  G06T1/20

Abstract: Embodiments are generally directed to a scalable memory interface for a graphical processor unit. An embodiment of an apparatus includes a graphical processing unit (GPU) including multiple autonomous engines; a common memory interface for the autonomous engines; and a memory management unit for the common memory interface, the memory management unit including multiple engine modules, wherein each of the engine modules includes a translation-lookaside buffer (TLB) that is dedicated to providing address translation for memory requests for a respective autonomous engine of the plurality of autonomous engines, and a TLB miss tracking mechanism that provides tracking for the respective autonomous engine.

公开(公告)号：US20190213140A1

公开(公告)日：2019-07-11

申请号：US15863347

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Altug Koker ,  Nicolas Kacevas ,  Parth S. Damani ,  David Standring

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/652 ,  G06F2212/68

Abstract: An apparatus to facilitate page translation is disclosed. The apparatus a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations and a page size table (PST) including a plurality of entries to store page size corresponding to each of the TLB entries.

公开(公告)号：US10347357B2

公开(公告)日：2019-07-09

申请号：US15495143

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Travis T. Schluessler ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Jonathan Kennedy

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/52 ,  G11C17/18 ,  G11C29/12 ,  G11C29/36 ,  G11C29/04

Abstract: Systems, apparatuses and methods provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, the technology identifies whether the redundant portion includes one or more remaining memory cells, and in response to an identification that the redundant portion includes the one or more remaining memory cells, the one or more remaining memory cells in the redundant portion are substituted for the one or more failed memory cells.

公开(公告)号：US10346946B2

公开(公告)日：2019-07-09

申请号：US16039509

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Akif Ali

IPC: G06T11/00 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06F15/08 ,  G06T15/80 ,  H04L12/933

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

公开(公告)号：US10325341B2

公开(公告)日：2019-06-18

申请号：US15493233

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Altug Koker ,  Joydeep Ray

IPC: G06T1/20 ,  G06T15/00

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing units and a pipeline manager to distribute a thread group to the multiple processing units, wherein the pipeline manager is to distribute the thread group as multiple thread sub-groups.