Abstract:
A phase-shift unit includes: a first substrate and a second substrate provided opposite to each other; a medium layer provided between the first substrate and the second substrate; a microstrip line disposed at a side of the second substrate facing towards the first substrate; and a grounding layer provided at a side of the first substrate facing towards the second substrate and formed with a via hole; wherein a projection of the via hole onto the second substrate and a projection of the microstrip line onto the second substrate have an overlapped area therebetween; and wherein the via hole is configured to feed a phase-shifted microwave signal out of the phase-shift unit, or feed a microwave signal into the phase-shift unit such that the microwave signal is phase-shifted.
Abstract:
A liquid crystal antenna and a manufacturing method thereof are disclosed. The liquid crystal antenna includes: an antenna array including a first substrate and a second substrate arranged opposite to each other and configured to change a phase of an electromagnetic wave signal fed into the liquid crystal antenna to transmit or receive a beam in a preset direction; and an inertial navigation element configured to determine a motion parameter of the liquid crystal antenna in a navigation coordinate system, the inertial navigation element is disposed on a side of the second substrate facing the first substrate; and the antenna array adjusts the preset direction according to the motion parameter acquired by the inertial navigation element.
Abstract:
A display panel includes: a base substrate; and a plurality of pixels on the base substrate, the plurality of pixels including a first pixel and a second pixel. The first pixel includes a first light-transmitting area and a first display area sequentially arranged in a first direction, and the second pixel includes a second light-transmitting area and a second display area sequentially arranged in the first direction. The first pixel and the second pixel are adjacent in a second direction, and the first light-transmitting area and the second light-transmitting area are adjacent in the second direction. The display panel further includes: a first gate line and a second gate line both arranged between the first light-transmitting area and the second light-transmitting area. The first light-transmitting area is contiguous to the first gate line, and the second light-transmitting area is contiguous to the second gate line.
Abstract:
The present disclosure is related to a substrate. The substrate may include a plurality of electrode patterns. Each of the plurality of the electrode patterns may include a first electrode and a plurality of second electrodes connected to the first electrode. A shape of second electrodes of an electrode pattern may be complementary to a shape of second electrodes of at least one electrode pattern adjacent to the electrode pattern.
Abstract:
The present disclosure provides a shift register unit. The shift register unit includes an input module, an output module and an output control module. The input module is connected to an input signal terminal, a first power supply signal terminal and a pull-up node, and is configured to transmit a first power supply signal to the pull-up node. The output module is connected to the pull-up node, a clock signal terminal and an output control node, and is configured to transmit a clock signal to the output control node. The output control module is connected to the output control node, the clock signal terminal and a signal output terminal, and is configured to transmit a signal of the output control node to the signal output terminal under the control of the clock signal.
Abstract:
There provide a pixel driving circuit and driving method thereof, an array substrate and display apparatus, wherein the pixel driving circuit comprises: a data line; a gate line; a first power supply line; a second power supply line; a light emitting device connected to the second power supply line; a driving transistor connected to the first power supply line; a storage capacitor having a first terminal connected to a gate of the driving transistor and configured to transfer information including the data voltage to the gate of the driving transistor; a resetting unit configured to reset a voltage across the storage capacitor as a predetermined signal voltage; a data writing unit configured to write information including the data voltage into the second terminal of the storage capacitor; a compensating unit configured to write information including a threshold voltage of the driving transistor and information of the first power supply voltage into the first terminal of the storage capacitor; and a light emitting control unit connected to the storage capacitor, the driving transistor and the light emitting device, and configured to control the driving transistor to drive the light emitting device to emit light.
Abstract:
GOA driving unit includes an input end, a starting module, a control module, an output module and a gate driving signal output end. The starting module is configured to, within a starting time period, input a triggering signal from the input end into the control module under the control of a first clock signal. The control module is configured to, within an output time period, output a second clock signal to the output module. The output module is configured to output a first level to the gate driving signal output end within the starting time period, output the second clock signal to the gate driving signal output end within the output time period, and output the first level to the gate driving signal output end within a maintenance time period. The first clock signal is of a phase reverse to the second clock signal.
Abstract:
The present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display apparatus. The shift register comprises an input circuit, a first output circuit, a second output circuit, and a negative voltage switching circuit. The input circuit has an input terminal configured to receive an input signal, an output terminal coupled to a first node, and a control terminal configured to receive a first clock signal. The first output circuit has an input terminal configured to receive a second clock signal, an output terminal coupled to an output signal terminal, and a control terminal coupled to the first node. The second output circuit has an input terminal configured to receive a first low level signal, an output terminal coupled to the output signal terminal, and a control terminal configured to receive a third clock signal. The negative voltage switching circuit has an input terminal configured to receive a second low level signal, an output terminal coupled to the first node, and a control terminal configured to receive a fourth clock signal.
Abstract:
The present disclosure relates to a field of display. Particularly, embodiments of the present invention disclose a shift register unit, a shift register, an array substrate and a display apparatus that enable the respective shift register units to be reset independently. The shift register unit includes a sampling part, an output part and a reset part, wherein the sampling part includes a first switching transistor and a second switching transistor, the output part includes a fifth switching transistor, a sixth switching transistor, a first capacitor and a second capacitor, and the reset part includes a third switching transistor and a fourth transistor.
Abstract:
A pixel circuit, a driving method, and a display apparatus, wherein the pixel circuit includes: a first switch transistor having a source connected to a data signal terminal, and a gate connected to a first control signal terminal; a first capacitor having a first terminal connected to a drain of the first switch transistor; a second capacitor having a first terminal connected to a second voltage signal terminal, and a second terminal connected to a second terminal of the first capacitor; a third capacitor having a first terminal connected to the first control signal terminal, and a second terminal connected to a gate of a driving transistor; a second switch transistor having a source connected to the gate of the driving transistor, a drain connected to a drain of the driving transistor, and a gate connected to the first control signal terminal; and a third, fourth, fifth and sixth switch transistors.