公开(公告)号：US20020166949A1

公开(公告)日：2002-11-14

申请号：US10119416

申请日：2002-04-08

Inventor： Satoshi Machida

IPC: H01L027/00

CPC classification number: H04N5/365 ,  G11C27/026 ,  H01L27/14609 ,  H04N5/363

Abstract: To provide a photoelectric converter in which random noise is reduced. In a photoelectric converter, an output terminal of a photoelectric converter means is connected to input terminals of a reset means and an amplifying means, a charge transfer means is connected to an output terminal of the amplifying means, another terminal of the charge transfer means is connected to a capacitor and a gate of a source follower amplifier, a source of the source follower amplifier is connected to a channel select means, another terminal of the channel select means is connected to a common signal line, and the common signal line is connected to a current source.

Abstract translation: 提供减少随机噪声的光电转换器。 在光电转换器中，光电转换器装置的输出端连接到复位装置和放大装置的输入端，电荷转移装置连接到放大装置的输出端，电荷转移装置的另一端 连接到源极跟随放大器的电容器和栅极，源极跟随放大器的源极连接到沟道选择装置，沟道选择装置的另一个端子连接到公共信号线，并且公共信号线被连接 到当前来源。

公开(公告)号：US20020135402A1

公开(公告)日：2002-09-26

申请号：US09992334

申请日：2001-11-06

Inventor： Satoru Miyabe ,  Yasuhiro Sugimoto

IPC: H03K005/00

CPC classification number: G11C27/026

Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow. There is provided a common phase feedback circuit 2, common phase feedback hold capacitors CF1 and CF2 of which are connected to input terminals IN1 and IN2 of a completely differential type operational amplifier circuit 1, during a sample period, by way of reset switches RS1 and RS2 connecting the input terminals IN1 and IN2 and output terminals OUT1 and OUT2 of the completely differential type operational amplifier circuit 1, the common phase feedback hold capacitors CF1 and CF2 are charged to thereby determine a balance point of a middle value of differential output signals from the output terminals OUT1 and OUT2 and during a hold period, the balance point of the middle value of the differential output signals is maintained by electric charge charged to the common phase feedback hold capacitors CF1 and CF2 regardless of the differential output signals.

Abstract translation: 在使用完全差分型运算放大器电路的采样保持电路中，为了提高运算稳定性，抑制差分输出信号的中间值的平衡点的变化，提高A / D转换器的稳定性和精度 是通过宪法实现的。 提供了一个公共相位反馈电路2，其公共相位反馈保持电容器CF1和CF2在采样周期期间通过复位开关RS1和...的连接到完全差分型运算放大器电路1的输入端IN1和IN2 连接完全差分型运算放大器电路1的输入端子IN1和IN2以及输出端子OUT1和OUT2的RS2，对公共相位反馈保持电容器CF1和CF2进行充电，从而确定差分输出信号的中间值的平衡点 输出端子OUT1和OUT2，并且在保持期间，不管差分输出信号如何，差分输出信号的中间值的平衡点由充电到公共相位反馈保持电容器CF1和CF2的电荷保持。

公开(公告)号：US20020063590A1

公开(公告)日：2002-05-30

申请号：US09921578

申请日：2001-08-06

Applicant: FUJITSU LIMITED

Inventor： Hiromi Nanba ,  Tohru Mizutani ,  Makoto Ikeshita ,  Masato Takeyabu

IPC: H03K005/12

CPC classification number: G11C27/026 ,  H03F1/30 ,  H03F2200/453 ,  H03K5/2481 ,  H03K5/249 ,  H03K19/00384

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD

Abstract translation: 评估电路16重复其输出VD被复位的处理，在电压Vi被逐步输入之后经过了各个时间t1和t2之后，重复给定次数复制电路11R的采样输出电压Vo之间的差异的处理 复制电路11R，并且差异被连续求和。 比较器电路20将差分累积电压VD与参考电压VS进行比较。 如果VD> VS，则偏置调整电路15在每给定时刻升压复制电路11R和调整电路11的偏置电流，并且如果VD

公开(公告)号：US06384758B1

公开(公告)日：2002-05-07

申请号：US09723956

申请日：2000-11-27

Applicant: Christopher Michalski ,  David Graham Nairn

Inventor： Christopher Michalski ,  David Graham Nairn

IPC: H03M100

CPC classification number: G11C27/026 ,  H03M1/167

Abstract: High-speed sampler methods and structures are provided to enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor Cs is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal Sin. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled to the capacitor's bottom plate to provide the output voltage Vout at the capacitor's top plate. Preferably, an output capacitor Co is coupled to the sampling capacitor Cs and charge from the sampling capacitor Cs is transferred to the output capacitor Co.

Abstract translation: 提供高速采样器方法和结构以增强输入信号Sin和对应的采样器输出电压Vout之间的相关性。 在采样时间段内启用输入缓冲器，并在保持时间段内禁用。 在采样时间段内，采样电容器Cs通过输入缓冲器和电容器的底板直接充电至对应于输入信号Sin的电荷。 在保持时间段中，禁用输入缓冲器与采样电容器Cs隔离，共模信号Scm直接耦合到电容器的底板，以提供电容器顶板上的输出电压Vout。 优选地，输出电容器Co耦合到采样电容器Cs，并且来自采样电容器Cs的电荷被传送到输出电容器Co

公开(公告)号：US06329260B1

公开(公告)日：2001-12-11

申请号：US09394802

申请日：1999-09-10

Applicant: Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

Inventor： Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

IPC: H01L21331

CPC classification number: G05F3/30 ,  G05F3/262 ,  G11C5/143 ,  G11C27/026 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03F2200/294 ,  H03G1/0082 ,  H03K5/15 ,  H03K17/223 ,  H03K2217/0018 ,  H03M1/162 ,  H03M1/365

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Abstract translation: 集成电路具有双二极管护城河形式的隔离结构。 P衬底在N +掩埋层8605的相对侧上具有P +掩埋层8601和8602.在一个二极管护套之后形成模拟器件，在另一个护城河之后形成数字CMOS器件。

公开(公告)号：US20010045847A1

公开(公告)日：2001-11-29

申请号：US09817969

申请日：2001-03-27

Inventor： Gian Hoogzaad ,  Eise Carel Dijkmans ,  Raf Lodewijk Jan Roovers

IPC: H03K005/00

CPC classification number: G11C27/026

Abstract: A track and hold amplifier for use in adc-converters comprises in succession an input buffer, a pn-junction switch and a hold capacitor. A feedback is provided between the hold capacitor and the input buffer and means are provided to disable the feedback during the hold mode.

Abstract translation: 用于adc转换器的跟踪和保持放大器包括输入缓冲器，pn结开关和保持电容器。 在保持电容器和输入缓冲器之间提供反馈，并提供用于在保持模式期间禁止反馈的装置。

公开(公告)号：US06320459B2

公开(公告)日：2001-11-20

申请号：US09739729

申请日：2000-12-18

Applicant: Rob McCullough

Inventor： Rob McCullough

IPC: H04B110

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03H19/004

Abstract: A filter system includes a low pass filter, a first summer circuit, a second low pass filter and a second summer circuit. The first low pass filter includes an input, an output, a storage means, a switching means and a control means. An input signal is placed on the input. An output signal is generated on the output. The storage means provides storage of a signal sample over time. The switching means, when closed, electrically couples the input to the first end of the storage means. The switching means, when open electrically isolates the input from the first end of the storage means. The control means controls the switching means. The control means generates a switching control signal. The switching control signal has a sampling frequency. A maximum cutoff frequency of the low pass filter is dependent on a value of a capacitance provided by the storage means, the sampling frequency, and a pulse width of the switching control signal. The first summer circuit subtracts the output signal from the input signal to produce a high pass output signal. The second low pass filter receives the high pass output signal and produces a bandpass filtered output. The second summer circuit subtracts the bandpass filtered output from the input signal to produce a notch filtered output.

Abstract translation: 滤波器系统包括低通滤波器，第一加法电路，第二低通滤波器和第二加法电路。 第一低通滤波器包括输入，输出，存储装置，开关装置和控制装置。 输入信号放在输入端。 在输出端产生输出信号。 存储装置随时间提供信号样本的存储。 切换装置在闭合时将输入端电耦合到存储装置的第一端。 开关装置当打开时将输入与存储装置的第一端电隔离。 控制装置控制切换装置。 控制装置产生开关控制信号。 开关控制信号具有采样频率。 低通滤波器的最大截止频率取决于由存储装置提供的电容值，采样频率和开关控制信号的脉冲宽度。 第一个夏季电路从输入信号中减去输出信号，产生高通输出信号。 第二低通滤波器接收高通输出信号并产生带通滤波输出。 第二个夏季电路从输入信号中减去带通滤波输出，产生陷波滤波输出。

公开(公告)号：US20010026175A1

公开(公告)日：2001-10-04

申请号：US09819616

申请日：2001-03-29

Applicant: KAWASAKI STEEL CORPORATION

Inventor： Masayuki Ueno

IPC: H03K005/00

CPC classification number: G11C27/026 ,  G11C27/024

Abstract: The purpose of the present invention is to prevent the charge stored in a hold capacitor from leaking via the switches connected to the electrode of the capacitor, in a sample-and-hold circuit, and to suppress the reduction in the voltage held in the capacitor, thereby improving the performance of the sample-and-hold circuit. The switches connected to the capacitor comprises two N-channel MOS transistors that are connected in series and are simultaneously turned on or off. During the period that the switches are in the OFF state, the potential at the interconnection node of the two transistors (one end of a first transistor) is set so as to be equal to that of the other end of the first transistor. Since the potential difference between the both ends of the first transistor thereby becomes zero, leakage currents via the first transistor is reduced, and charge leakage in the capacitor can be prevented.

Abstract translation: 本发明的目的是防止存储在保持电容器中的电荷通过连接到电容器的电极的开关在采样和保持电路中泄漏，并且抑制保持在电容器中的电压的降低 ，从而提高采样保持电路的性能。 连接到电容器的开关包括串联连接并同时导通或截止的两个N沟道MOS晶体管。 在开关处于截止状态的期间，将两个晶体管（第一晶体管的一端）的互连节点处的电位设定为与第一晶体管另一端的电位相等。 由于第一晶体管的两端之间的电位差由此变为零，所以经由第一晶体管的漏电流减小，并且可以防止电容器中的电荷泄漏。

公开(公告)号：US06275076B1

公开(公告)日：2001-08-14

申请号：US09526200

申请日：2000-03-15

Applicant: Laurent Simony

Inventor： Laurent Simony

IPC: G11C2702

CPC classification number: G11C27/026

Abstract: The proposed sample-and-hold device using a complementary bipolar technology comprises a follower input stage having an input receiving a voltage Vin to be sampled, at least one sampling circuit having a switching stage to be placed either in a first state called a “follower” state where its output follows the potential at its signal input or in a second state called an “isolated” state where its output is isolated from it signal input, the output of the switching stage being connected to the base of a first follower transistor whose emitter is connected to a terminal of an output sampling capacitor, the sampling circuit furthermore comprising a second transistor, having its emitter supplied by a current source and having its base connected to a potential copying that of the terminal of the output sampling capacitor, and a third transistor controlled by the digital command so as to be crossed by a current when the switching stage is in the >, and so as to be off when the switching stage is in the > state, the third transistor having its emitter connected to the base of the first transistor and its base connected to the emitter of the second transistor. Application to analog-digital converters, analog signal processing systems.

Abstract translation: 所提出的使用互补双极性技术的采样和保持装置包括：跟随器输入级，其具有接收要采样的电压Vin的输入端，至少一个采样电路，其具有将被放置在称为“跟随器”的第一状态的开关级 “状态，其输出跟随其信号输入或称为”隔离“状态的第二状态的电位，其中其输出与信号输入隔离，开关级的输出连接到第一跟随器晶体管的基极， 发射极连接到输出采样电容器的端子，该采样电路还包括第二晶体管，其第二晶体管具有由电流源提供的发射极，其基极连接到输出采样电容器的端子的潜在复制，以及 第三晶体管由数字命令控制，以便当开关级处于“隔离状态”时被电流交叉，并且当t 他的开关级处于“跟随器”状态，第三晶体管的发射极连接到第一晶体管的基极，其基极连接到第二晶体管的发射极。 应用于模数转换器，模拟信号处理系统。

公开(公告)号：US06255865B1

公开(公告)日：2001-07-03

申请号：US09433838

申请日：1999-11-03

Applicant: Ion E. Opris

Inventor： Ion E. Opris

IPC: G11C2702

CPC classification number: A63F3/081 ,  G06Q20/04 ,  G07F17/3244 ,  G07F17/3248 ,  G07F17/3262 ,  G11C27/026

Abstract: A method and apparatus for an improved track-and-hold circuit is disclosed. By utilizing an amplifier connected to the input signal in combination with, in essence, a replica of the track-and-hold sampling transistor, a track-and-hold technique that reduces distortion and nonlinearities in the sampling process is achieved.

Abstract translation: 公开了一种改进的跟踪和保持电路的方法和装置。 通过利用连接到输入信号的放大器，本质上是跟踪和保持采样晶体管的复制品，实现了减少采样过程中的失真和非线性的跟踪和保持技术。