公开(公告)号：US11373981B2

公开(公告)日：2022-06-28

申请号：US16786969

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/60 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

公开(公告)号：US11322477B2

公开(公告)日：2022-05-03

申请号：US16896219

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Nien-Fang Wu ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

公开(公告)号：US11257787B2

公开(公告)日：2022-02-22

申请号：US16876140

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

公开(公告)号：US11164848B2

公开(公告)日：2021-11-02

申请号：US16737869

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chuan-An Cheng

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

公开(公告)号：US20210249380A1

公开(公告)日：2021-08-12

申请号：US16787031

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00

Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.

公开(公告)号：US11056438B2

公开(公告)日：2021-07-06

申请号：US16658131

申请日：2019-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Nien-Fang Wu ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Semiconductor packages and method of forming the same are disclosed. One of the semiconductor packages includes a first die, a second die, a through via and a dielectric encapsulation. The second die is bonded to the first die. The through via is disposed aside the second die and electrically connected to the first die. The through via includes a step-shaped sidewall. The dielectric encapsulation encapsulates the second die and the through via.

公开(公告)号：US20210098323A1

公开(公告)日：2021-04-01

申请号：US17120859

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen ,  Hsien-Wei Chen ,  Tzuan-Horng Liu

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/48 ,  H01L23/522

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

公开(公告)号：US20210091084A1

公开(公告)日：2021-03-25

申请号：US16806470

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L27/105 ,  H01L27/146

Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

公开(公告)号：US20210066248A1

公开(公告)日：2021-03-04

申请号：US16786969

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/60 ,  H01L21/683 ,  H01L25/00

Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

公开(公告)号：US20200294984A1

公开(公告)日：2020-09-17

申请号：US16888800

申请日：2020-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Chi-Hwang Tai

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/18 ,  H01L23/544

Abstract: A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.